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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia64   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_ia64_ASM_H_
  36. #define KERN_ia64_ASM_H_
  37.  
  38. #include <config.h>
  39. #include <arch/types.h>
  40. #include <arch/register.h>
  41.  
  42.  
  43. #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
  44.  
  45. static inline void  outb(uint64_t port,uint8_t v)
  46. {
  47.     *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
  48.  
  49.     asm volatile ("mf\n" ::: "memory");
  50. }
  51.  
  52.  
  53. static inline uint8_t inb(uint64_t port)
  54. {
  55.     asm volatile ("mf\n" ::: "memory");
  56.  
  57.     return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
  58. }
  59.  
  60.  
  61.  
  62. /** Return base address of current stack
  63.  *
  64.  * Return the base address of the current stack.
  65.  * The stack is assumed to be STACK_SIZE long.
  66.  * The stack must start on page boundary.
  67.  */
  68. static inline uintptr_t get_stack_base(void)
  69. {
  70.     uint64_t v;
  71.  
  72.     asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
  73.    
  74.     return v;
  75. }
  76.  
  77. /** Return Processor State Register.
  78.  *
  79.  * @return PSR.
  80.  */
  81. static inline uint64_t psr_read(void)
  82. {
  83.     uint64_t v;
  84.    
  85.     asm volatile ("mov %0 = psr\n" : "=r" (v));
  86.    
  87.     return v;
  88. }
  89.  
  90. /** Read IVA (Interruption Vector Address).
  91.  *
  92.  * @return Return location of interruption vector table.
  93.  */
  94. static inline uint64_t iva_read(void)
  95. {
  96.     uint64_t v;
  97.    
  98.     asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
  99.    
  100.     return v;
  101. }
  102.  
  103. /** Write IVA (Interruption Vector Address) register.
  104.  *
  105.  * @param v New location of interruption vector table.
  106.  */
  107. static inline void iva_write(uint64_t v)
  108. {
  109.     asm volatile ("mov cr.iva = %0\n" : : "r" (v));
  110. }
  111.  
  112.  
  113. /** Read IVR (External Interrupt Vector Register).
  114.  *
  115.  * @return Highest priority, pending, unmasked external interrupt vector.
  116.  */
  117. static inline uint64_t ivr_read(void)
  118. {
  119.     uint64_t v;
  120.    
  121.     asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
  122.    
  123.     return v;
  124. }
  125.  
  126. /** Write ITC (Interval Timer Counter) register.
  127.  *
  128.  * @param v New counter value.
  129.  */
  130. static inline void itc_write(uint64_t v)
  131. {
  132.     asm volatile ("mov ar.itc = %0\n" : : "r" (v));
  133. }
  134.  
  135. /** Read ITC (Interval Timer Counter) register.
  136.  *
  137.  * @return Current counter value.
  138.  */
  139. static inline uint64_t itc_read(void)
  140. {
  141.     uint64_t v;
  142.    
  143.     asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
  144.    
  145.     return v;
  146. }
  147.  
  148. /** Write ITM (Interval Timer Match) register.
  149.  *
  150.  * @param v New match value.
  151.  */
  152. static inline void itm_write(uint64_t v)
  153. {
  154.     asm volatile ("mov cr.itm = %0\n" : : "r" (v));
  155. }
  156.  
  157. /** Read ITM (Interval Timer Match) register.
  158.  *
  159.  * @return Match value.
  160.  */
  161. static inline uint64_t itm_read(void)
  162. {
  163.     uint64_t v;
  164.    
  165.     asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
  166.    
  167.     return v;
  168. }
  169.  
  170. /** Read ITV (Interval Timer Vector) register.
  171.  *
  172.  * @return Current vector and mask bit.
  173.  */
  174. static inline uint64_t itv_read(void)
  175. {
  176.     uint64_t v;
  177.    
  178.     asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
  179.    
  180.     return v;
  181. }
  182.  
  183. /** Write ITV (Interval Timer Vector) register.
  184.  *
  185.  * @param v New vector and mask bit.
  186.  */
  187. static inline void itv_write(uint64_t v)
  188. {
  189.     asm volatile ("mov cr.itv = %0\n" : : "r" (v));
  190. }
  191.  
  192. /** Write EOI (End Of Interrupt) register.
  193.  *
  194.  * @param v This value is ignored.
  195.  */
  196. static inline void eoi_write(uint64_t v)
  197. {
  198.     asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
  199. }
  200.  
  201. /** Read TPR (Task Priority Register).
  202.  *
  203.  * @return Current value of TPR.
  204.  */
  205. static inline uint64_t tpr_read(void)
  206. {
  207.     uint64_t v;
  208.  
  209.     asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
  210.    
  211.     return v;
  212. }
  213.  
  214. /** Write TPR (Task Priority Register).
  215.  *
  216.  * @param v New value of TPR.
  217.  */
  218. static inline void tpr_write(uint64_t v)
  219. {
  220.     asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
  221. }
  222.  
  223. /** Disable interrupts.
  224.  *
  225.  * Disable interrupts and return previous
  226.  * value of PSR.
  227.  *
  228.  * @return Old interrupt priority level.
  229.  */
  230. static ipl_t interrupts_disable(void)
  231. {
  232.     uint64_t v;
  233.    
  234.     asm volatile (
  235.         "mov %0 = psr\n"
  236.         "rsm %1\n"
  237.         : "=r" (v)
  238.         : "i" (PSR_I_MASK)
  239.     );
  240.    
  241.     return (ipl_t) v;
  242. }
  243.  
  244. /** Enable interrupts.
  245.  *
  246.  * Enable interrupts and return previous
  247.  * value of PSR.
  248.  *
  249.  * @return Old interrupt priority level.
  250.  */
  251. static ipl_t interrupts_enable(void)
  252. {
  253.     uint64_t v;
  254.    
  255.     asm volatile (
  256.         "mov %0 = psr\n"
  257.         "ssm %1\n"
  258.         ";;\n"
  259.         "srlz.d\n"
  260.         : "=r" (v)
  261.         : "i" (PSR_I_MASK)
  262.     );
  263.    
  264.     return (ipl_t) v;
  265. }
  266.  
  267. /** Restore interrupt priority level.
  268.  *
  269.  * Restore PSR.
  270.  *
  271.  * @param ipl Saved interrupt priority level.
  272.  */
  273. static inline void interrupts_restore(ipl_t ipl)
  274. {
  275.     if (ipl & PSR_I_MASK)
  276.         (void) interrupts_enable();
  277.     else
  278.         (void) interrupts_disable();
  279. }
  280.  
  281. /** Return interrupt priority level.
  282.  *
  283.  * @return PSR.
  284.  */
  285. static inline ipl_t interrupts_read(void)
  286. {
  287.     return (ipl_t) psr_read();
  288. }
  289.  
  290. /** Disable protection key checking. */
  291. static inline void pk_disable(void)
  292. {
  293.     asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
  294. }
  295.  
  296. extern void cpu_halt(void);
  297. extern void cpu_sleep(void);
  298. extern void asm_delay_loop(uint32_t t);
  299.  
  300. extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
  301.  
  302. #endif
  303.  
  304. /** @}
  305.  */
  306.