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  1. /*
  2.  * Copyright (c) 2006 Martin Decky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia32xen
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/pm.h>
  36. #include <config.h>
  37. #include <arch/types.h>
  38. #include <arch/interrupt.h>
  39. #include <arch/asm.h>
  40. #include <arch/context.h>
  41. #include <panic.h>
  42. #include <arch/mm/page.h>
  43. #include <mm/slab.h>
  44. #include <memstr.h>
  45. #include <interrupt.h>
  46.  
  47. /*
  48.  * Early ia32xen configuration functions and data structures.
  49.  */
  50.  
  51. /*
  52.  * We have no use for segmentation so we set up flat mode. In this
  53.  * mode, we use, for each privilege level, two segments spanning the
  54.  * whole memory. One is for code and one is for data.
  55.  *
  56.  * One is for GS register which holds pointer to the TLS thread
  57.  * structure in it's base.
  58.  */
  59. descriptor_t gdt[GDT_ITEMS] = {
  60.     /* NULL descriptor */
  61.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  62.     /* KTEXT descriptor */
  63.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  64.     /* KDATA descriptor */
  65.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  66.     /* UTEXT descriptor */
  67.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  68.     /* UDATA descriptor */
  69.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  70.     /* TSS descriptor - set up will be completed later */
  71.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  72.     /* TLS descriptor */
  73.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  74. };
  75.  
  76. static trap_info_t traps[IDT_ITEMS + 1];
  77.  
  78. static tss_t tss;
  79.  
  80. tss_t *tss_p = NULL;
  81.  
  82. /* gdtr is changed by kmp before next CPU is initialized */
  83. ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
  84. ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
  85.  
  86. void gdt_setbase(descriptor_t *d, uintptr_t base)
  87. {
  88.     d->base_0_15 = base & 0xffff;
  89.     d->base_16_23 = ((base) >> 16) & 0xff;
  90.     d->base_24_31 = ((base) >> 24) & 0xff;
  91. }
  92.  
  93. void gdt_setlimit(descriptor_t *d, uint32_t limit)
  94. {
  95.     d->limit_0_15 = limit & 0xffff;
  96.     d->limit_16_19 = (limit >> 16) & 0xf;
  97. }
  98.  
  99. void tss_initialize(tss_t *t)
  100. {
  101.     memsetb(t, sizeof(struct tss), 0);
  102. }
  103.  
  104. static void trap(void)
  105. {
  106. }
  107.  
  108. void traps_init(void)
  109. {
  110.     index_t i;
  111.    
  112.     for (i = 0; i < IDT_ITEMS; i++) {
  113.         traps[i].vector = i;
  114.        
  115.         if (i == VECTOR_SYSCALL)
  116.             traps[i].flags = 3;
  117.         else
  118.             traps[i].flags = 0;
  119.        
  120.         traps[i].cs = XEN_CS;
  121.         traps[i].address = trap;
  122.     }
  123.     traps[IDT_ITEMS].vector = 0;
  124.     traps[IDT_ITEMS].flags = 0;
  125.     traps[IDT_ITEMS].cs = 0;
  126.     traps[IDT_ITEMS].address = NULL;
  127. }
  128.  
  129.  
  130. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  131. static void clean_IOPL_NT_flags(void)
  132. {
  133. //  asm volatile (
  134. //      "pushfl\n"
  135. //      "pop %%eax\n"
  136. //      "and $0xffff8fff, %%eax\n"
  137. //      "push %%eax\n"
  138. //      "popfl\n"
  139. //      : : : "eax"
  140. //  );
  141. }
  142.  
  143. /* Clean AM(18) flag in CR0 register */
  144. static void clean_AM_flag(void)
  145. {
  146. //  asm volatile (
  147. //      "mov %%cr0, %%eax\n"
  148. //      "and $0xfffbffff, %%eax\n"
  149. //      "mov %%eax, %%cr0\n"
  150. //      : : : "eax"
  151. //  );
  152. }
  153.  
  154. void pm_init(void)
  155. {
  156.     descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
  157.  
  158. //  gdtr_load(&gdtr);
  159.    
  160.     if (config.cpu_active == 1) {
  161.         traps_init();
  162.         xen_set_trap_table(traps);
  163.         /*
  164.          * NOTE: bootstrap CPU has statically allocated TSS, because
  165.          * the heap hasn't been initialized so far.
  166.          */
  167.         tss_p = &tss;
  168.     } else {
  169.         tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
  170.         if (!tss_p)
  171.             panic("could not allocate TSS\n");
  172.     }
  173.  
  174. //  tss_initialize(tss_p);
  175.    
  176.     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
  177.     gdt_p[TSS_DES].special = 1;
  178.     gdt_p[TSS_DES].granularity = 0;
  179.    
  180.     gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
  181.     gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
  182.  
  183.     /*
  184.      * As of this moment, the current CPU has its own GDT pointing
  185.      * to its own TSS. We just need to load the TR register.
  186.      */
  187. //  tr_load(selector(TSS_DES));
  188.    
  189.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
  190.     clean_AM_flag();          /* Disable alignment check */
  191. }
  192.  
  193. void set_tls_desc(uintptr_t tls)
  194. {
  195.     ptr_16_32_t cpugdtr;
  196.     descriptor_t *gdt_p;
  197.  
  198.     gdtr_store(&cpugdtr);
  199.     gdt_p = (descriptor_t *) cpugdtr.base;
  200.     gdt_setbase(&gdt_p[TLS_DES], tls);
  201.     /* Reload gdt register to update GS in CPU */
  202.     gdtr_load(&cpugdtr);
  203. }
  204.  
  205. /** @}
  206.  */
  207.