Subversion Repositories HelenOS

Rev

Rev 2467 | Rev 3386 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (c) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup mips32mm   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_mips32_PAGE_H_
  36. #define KERN_mips32_PAGE_H_
  37.  
  38. #include <arch/mm/frame.h>
  39.  
  40. #define PAGE_WIDTH  FRAME_WIDTH
  41. #define PAGE_SIZE   FRAME_SIZE
  42.  
  43. #ifndef __ASM__
  44. #   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
  45. #   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
  46. #else
  47. #   define KA2PA(x) ((x) - 0x80000000)
  48. #   define PA2KA(x) ((x) + 0x80000000)
  49. #endif
  50.  
  51. #ifdef KERNEL
  52.  
  53. /*
  54.  * Implementation of generic 4-level page table interface.
  55.  *
  56.  * Page table layout:
  57.  * - 32-bit virtual addresses
  58.  * - Offset is 14 bits => pages are 16K long
  59.  * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
  60.  *   4 bytes long
  61.  * - PTE's replace EntryLo v (valid) bit with p (present) bit
  62.  * - PTE's use only one bit to distinguish between cacheable and uncacheable
  63.  *   mappings
  64.  * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
  65.  *   the p bit is cleared
  66.  * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
  67.  *   and bit A (accessed)
  68.  * - PTL0 has 64 entries (6 bits)
  69.  * - PTL1 is not used
  70.  * - PTL2 is not used
  71.  * - PTL3 has 4096 entries (12 bits)
  72.  */
  73.  
  74. /* Macros describing number of entries in each level. */
  75. #define PTL0_ENTRIES_ARCH   64
  76. #define PTL1_ENTRIES_ARCH   0
  77. #define PTL2_ENTRIES_ARCH   0
  78. #define PTL3_ENTRIES_ARCH   4096
  79.  
  80. /* Macros describing size of page tables in each level. */
  81. #define PTL0_SIZE_ARCH      ONE_FRAME
  82. #define PTL1_SIZE_ARCH      0
  83. #define PTL2_SIZE_ARCH      0
  84. #define PTL3_SIZE_ARCH      ONE_FRAME
  85.  
  86. /* Macros calculating entry indices for each level. */
  87. #define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
  88. #define PTL1_INDEX_ARCH(vaddr)  0
  89. #define PTL2_INDEX_ARCH(vaddr)  0
  90. #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
  91.  
  92. /* Set accessor for PTL0 address. */
  93. #define SET_PTL0_ADDRESS_ARCH(ptl0)
  94.  
  95. /* Get PTE address accessors for each level. */
  96. #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
  97.     (((pte_t *) (ptl0))[(i)].pfn << 12)
  98. #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
  99.     (ptl1)
  100. #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
  101.     (ptl2)
  102. #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
  103.     (((pte_t *) (ptl3))[(i)].pfn << 12)
  104.  
  105. /* Set PTE address accessors for each level. */
  106. #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
  107.     (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
  108. #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
  109. #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
  110. #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
  111.     (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
  112.  
  113. /* Get PTE flags accessors for each level. */
  114. #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
  115.     get_pt_flags((pte_t *) (ptl0), (index_t) (i))
  116. #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
  117.     PAGE_PRESENT
  118. #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
  119.     PAGE_PRESENT
  120. #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
  121.     get_pt_flags((pte_t *) (ptl3), (index_t) (i))
  122.  
  123. /* Set PTE flags accessors for each level. */
  124. #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
  125.     set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
  126. #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
  127. #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
  128. #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
  129.     set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
  130.  
  131. /* Last-level info macros. */
  132. #define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
  133. #define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
  134. #define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
  135. #define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
  136. #define PTE_EXECUTABLE_ARCH(pte)        1
  137.  
  138. #ifndef __ASM__
  139.  
  140. #include <mm/mm.h>
  141. #include <arch/exception.h>
  142.  
  143. static inline int get_pt_flags(pte_t *pt, index_t i)
  144. {
  145.     pte_t *p = &pt[i];
  146.    
  147.     return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
  148.         ((!p->p) << PAGE_PRESENT_SHIFT) |
  149.         (1 << PAGE_USER_SHIFT) |
  150.         (1 << PAGE_READ_SHIFT) |
  151.         ((p->w) << PAGE_WRITE_SHIFT) |
  152.         (1 << PAGE_EXEC_SHIFT) |
  153.         (p->g << PAGE_GLOBAL_SHIFT));
  154. }
  155.  
  156. static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
  157. {
  158.     pte_t *p = &pt[i];
  159.    
  160.     p->cacheable = (flags & PAGE_CACHEABLE) != 0;
  161.     p->p = !(flags & PAGE_NOT_PRESENT);
  162.     p->g = (flags & PAGE_GLOBAL) != 0;
  163.     p->w = (flags & PAGE_WRITE) != 0;
  164.    
  165.     /*
  166.      * Ensure that valid entries have at least one bit set.
  167.      */
  168.     p->soft_valid = 1;
  169. }
  170.  
  171. extern void page_arch_init(void);
  172.  
  173. #endif /* __ASM__ */
  174.  
  175. #endif /* KERNEL */
  176.  
  177. #endif
  178.  
  179. /** @}
  180.  */
  181.