Subversion Repositories HelenOS

Rev

Rev 1859 | Rev 1864 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/tlb.h>
  36. #include <mm/tlb.h>
  37. #include <mm/as.h>
  38. #include <mm/asid.h>
  39. #include <arch/mm/frame.h>
  40. #include <arch/mm/page.h>
  41. #include <arch/mm/mmu.h>
  42. #include <arch/interrupt.h>
  43. #include <arch.h>
  44. #include <print.h>
  45. #include <arch/types.h>
  46. #include <typedefs.h>
  47. #include <config.h>
  48. #include <arch/trap/trap.h>
  49. #include <panic.h>
  50. #include <arch/asm.h>
  51. #include <symtab.h>
  52.  
  53. static void dtlb_pte_copy(pte_t *t, bool ro);
  54. static void itlb_pte_copy(pte_t *t);
  55. static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str);
  56. static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
  57. static void do_fast_data_access_protection_fault(istate_t *istate, const char *str);
  58.  
  59. char *context_encoding[] = {
  60.     "Primary",
  61.     "Secondary",
  62.     "Nucleus",
  63.     "Reserved"
  64. };
  65.  
  66. void tlb_arch_init(void)
  67. {
  68.     /*
  69.      * TLBs are actually initialized early
  70.      * in start.S.
  71.      */
  72. }
  73.  
  74. /** Insert privileged mapping into DMMU TLB.
  75.  *
  76.  * @param page Virtual page address.
  77.  * @param frame Physical frame address.
  78.  * @param pagesize Page size.
  79.  * @param locked True for permanent mappings, false otherwise.
  80.  * @param cacheable True if the mapping is cacheable, false otherwise.
  81.  */
  82. void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
  83. {
  84.     tlb_tag_access_reg_t tag;
  85.     tlb_data_t data;
  86.     page_address_t pg;
  87.     frame_address_t fr;
  88.  
  89.     pg.address = page;
  90.     fr.address = frame;
  91.  
  92.     tag.value = ASID_KERNEL;
  93.     tag.vpn = pg.vpn;
  94.  
  95.     dtlb_tag_access_write(tag.value);
  96.  
  97.     data.value = 0;
  98.     data.v = true;
  99.     data.size = pagesize;
  100.     data.pfn = fr.pfn;
  101.     data.l = locked;
  102.     data.cp = cacheable;
  103.     data.cv = cacheable;
  104.     data.p = true;
  105.     data.w = true;
  106.     data.g = true;
  107.  
  108.     dtlb_data_in_write(data.value);
  109. }
  110.  
  111. /** Copy PTE to TLB.
  112.  *
  113.  * @param t Page Table Entry to be copied.
  114.  * @param ro If true, the entry will be created read-only, regardless of its w field.
  115.  */
  116. void dtlb_pte_copy(pte_t *t, bool ro)
  117. {
  118.     tlb_tag_access_reg_t tag;
  119.     tlb_data_t data;
  120.     page_address_t pg;
  121.     frame_address_t fr;
  122.  
  123.     pg.address = t->page;
  124.     fr.address = t->frame;
  125.  
  126.     tag.value = 0;
  127.     tag.context = t->as->asid;
  128.     tag.vpn = pg.vpn;
  129.    
  130.     dtlb_tag_access_write(tag.value);
  131.    
  132.     data.value = 0;
  133.     data.v = true;
  134.     data.size = PAGESIZE_8K;
  135.     data.pfn = fr.pfn;
  136.     data.l = false;
  137.     data.cp = t->c;
  138.     data.cv = t->c;
  139.     data.p = t->p;
  140.     data.w = ro ? false : t->w;
  141.     data.g = t->g;
  142.    
  143.     dtlb_data_in_write(data.value);
  144. }
  145.  
  146. void itlb_pte_copy(pte_t *t)
  147. {
  148.     tlb_tag_access_reg_t tag;
  149.     tlb_data_t data;
  150.     page_address_t pg;
  151.     frame_address_t fr;
  152.  
  153.     pg.address = t->page;
  154.     fr.address = t->frame;
  155.  
  156.     tag.value = 0;
  157.     tag.context = t->as->asid;
  158.     tag.vpn = pg.vpn;
  159.    
  160.     itlb_tag_access_write(tag.value);
  161.    
  162.     data.value = 0;
  163.     data.v = true;
  164.     data.size = PAGESIZE_8K;
  165.     data.pfn = fr.pfn;
  166.     data.l = false;
  167.     data.cp = t->c;
  168.     data.cv = t->c;
  169.     data.p = t->p;
  170.     data.w = false;
  171.     data.g = t->g;
  172.    
  173.     itlb_data_in_write(data.value);
  174. }
  175.  
  176. /** ITLB miss handler. */
  177. void fast_instruction_access_mmu_miss(int n, istate_t *istate)
  178. {
  179.     uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
  180.     pte_t *t;
  181.  
  182.     page_table_lock(AS, true);
  183.     t = page_mapping_find(AS, va);
  184.     if (t && PTE_EXECUTABLE(t)) {
  185.         /*
  186.          * The mapping was found in the software page hash table.
  187.          * Insert it into ITLB.
  188.          */
  189.         t->a = true;
  190.         itlb_pte_copy(t);
  191.         page_table_unlock(AS, true);
  192.     } else {
  193.         /*
  194.          * Forward the page fault to the address space page fault handler.
  195.          */    
  196.         page_table_unlock(AS, true);
  197.         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
  198.             do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
  199.         }
  200.     }
  201. }
  202.  
  203. /** DTLB miss handler.
  204.  *
  205.  * Note that some faults (e.g. kernel faults) were already resolved
  206.  * by the low-level, assembly language part of the fast_data_access_mmu_miss
  207.  * handler.
  208.  */
  209. void fast_data_access_mmu_miss(int n, istate_t *istate)
  210. {
  211.     tlb_tag_access_reg_t tag;
  212.     uintptr_t va;
  213.     pte_t *t;
  214.  
  215.     tag.value = dtlb_tag_access_read();
  216.     va = tag.vpn * PAGE_SIZE;
  217.     if (tag.context == ASID_KERNEL) {
  218.         if (!tag.vpn) {
  219.             /* NULL access in kernel */
  220.             do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
  221.         }
  222.         do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault.");
  223.     }
  224.  
  225.     page_table_lock(AS, true);
  226.     t = page_mapping_find(AS, va);
  227.     if (t) {
  228.         /*
  229.          * The mapping was found in the software page hash table.
  230.          * Insert it into DTLB.
  231.          */
  232.         t->a = true;
  233.         dtlb_pte_copy(t, true);
  234.         page_table_unlock(AS, true);
  235.     } else {
  236.         /*
  237.          * Forward the page fault to the address space page fault handler.
  238.          */    
  239.         page_table_unlock(AS, true);
  240.         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
  241.             do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
  242.         }
  243.     }
  244. }
  245.  
  246. /** DTLB protection fault handler. */
  247. void fast_data_access_protection(int n, istate_t *istate)
  248. {
  249.     tlb_tag_access_reg_t tag;
  250.     uintptr_t va;
  251.     pte_t *t;
  252.  
  253.     tag.value = dtlb_tag_access_read();
  254.     va = tag.vpn * PAGE_SIZE;
  255.  
  256.     page_table_lock(AS, true);
  257.     t = page_mapping_find(AS, va);
  258.     if (t && PTE_WRITABLE(t)) {
  259.         /*
  260.          * The mapping was found in the software page hash table and is writable.
  261.          * Demap the old mapping and insert an updated mapping into DTLB.
  262.          */
  263.         t->a = true;
  264.         t->d = true;
  265.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
  266.         dtlb_pte_copy(t, false);
  267.         page_table_unlock(AS, true);
  268.     } else {
  269.         /*
  270.          * Forward the page fault to the address space page fault handler.
  271.          */    
  272.         page_table_unlock(AS, true);
  273.         if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
  274.             do_fast_data_access_protection_fault(istate, __FUNCTION__);
  275.         }
  276.     }
  277. }
  278.  
  279. /** Print contents of both TLBs. */
  280. void tlb_print(void)
  281. {
  282.     int i;
  283.     tlb_data_t d;
  284.     tlb_tag_read_reg_t t;
  285.    
  286.     printf("I-TLB contents:\n");
  287.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  288.         d.value = itlb_data_access_read(i);
  289.         t.value = itlb_tag_read_read(i);
  290.        
  291.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  292.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  293.     }
  294.  
  295.     printf("D-TLB contents:\n");
  296.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  297.         d.value = dtlb_data_access_read(i);
  298.         t.value = dtlb_tag_read_read(i);
  299.        
  300.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  301.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  302.     }
  303.  
  304. }
  305.  
  306. void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
  307. {
  308.     char *tpc_str = get_symtab_entry(istate->tpc);
  309.  
  310.     printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
  311.     panic("%s\n", str);
  312. }
  313.  
  314. void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str)
  315. {
  316.     tlb_tag_access_reg_t tag;
  317.     uintptr_t va;
  318.     char *tpc_str = get_symtab_entry(istate->tpc);
  319.  
  320.     tag.value = dtlb_tag_access_read();
  321.     va = tag.vpn * PAGE_SIZE;
  322.  
  323.     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
  324.     printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
  325.     panic("%s\n", str);
  326. }
  327.  
  328. void do_fast_data_access_protection_fault(istate_t *istate, const char *str)
  329. {
  330.     tlb_tag_access_reg_t tag;
  331.     uintptr_t va;
  332.     char *tpc_str = get_symtab_entry(istate->tpc);
  333.  
  334.     tag.value = dtlb_tag_access_read();
  335.     va = tag.vpn * PAGE_SIZE;
  336.  
  337.     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
  338.     printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
  339.     panic("%s\n", str);
  340. }
  341.  
  342. /** Invalidate all unlocked ITLB and DTLB entries. */
  343. void tlb_invalidate_all(void)
  344. {
  345.     int i;
  346.     tlb_data_t d;
  347.     tlb_tag_read_reg_t t;
  348.  
  349.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  350.         d.value = itlb_data_access_read(i);
  351.         if (!d.l) {
  352.             t.value = itlb_tag_read_read(i);
  353.             d.v = false;
  354.             itlb_tag_access_write(t.value);
  355.             itlb_data_access_write(i, d.value);
  356.         }
  357.     }
  358.    
  359.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  360.         d.value = dtlb_data_access_read(i);
  361.         if (!d.l) {
  362.             t.value = dtlb_tag_read_read(i);
  363.             d.v = false;
  364.             dtlb_tag_access_write(t.value);
  365.             dtlb_data_access_write(i, d.value);
  366.         }
  367.     }
  368.    
  369. }
  370.  
  371. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  372.  *
  373.  * @param asid Address Space ID.
  374.  */
  375. void tlb_invalidate_asid(asid_t asid)
  376. {
  377.     tlb_context_reg_t sc_save, ctx;
  378.    
  379.     ctx.v = sc_save.v = mmu_secondary_context_read();
  380.     ctx.context = asid;
  381.     mmu_secondary_context_write(ctx.v);
  382.    
  383.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
  384.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
  385.    
  386.     mmu_secondary_context_write(sc_save.v);
  387. }
  388.  
  389. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  390.  *
  391.  * @param asid Address Space ID.
  392.  * @param page First page which to sweep out from ITLB and DTLB.
  393.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  394.  */
  395. void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
  396. {
  397.     int i;
  398.     tlb_context_reg_t sc_save, ctx;
  399.    
  400.     ctx.v = sc_save.v = mmu_secondary_context_read();
  401.     ctx.context = asid;
  402.     mmu_secondary_context_write(ctx.v);
  403.    
  404.     for (i = 0; i < cnt; i++) {
  405.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
  406.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
  407.     }
  408.    
  409.     mmu_secondary_context_write(sc_save.v);
  410. }
  411.  
  412. /** @}
  413.  */
  414.