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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/pm.h>
  30. #include <config.h>
  31. #include <arch/types.h>
  32. #include <typedefs.h>
  33. #include <arch/interrupt.h>
  34. #include <arch/asm.h>
  35. #include <arch/context.h>
  36. #include <panic.h>
  37. #include <arch/mm/page.h>
  38.  
  39. /*
  40.  * Early ia32 configuration functions and data structures.
  41.  */
  42.  
  43. /*
  44.  * We have no use for segmentation so we set up flat mode. In this
  45.  * mode, we use, for each privilege level, two segments spanning the
  46.  * whole memory. One is for code and one is for data.
  47.  */
  48. struct descriptor gdt[GDT_ITEMS] = {
  49.     /* NULL descriptor */
  50.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  51.     /* KTEXT descriptor */
  52.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  53.     /* KDATA descriptor */
  54.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  55.     /* UTEXT descriptor */
  56.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  57.     /* UDATA descriptor */
  58.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  59.     /* TSS descriptor - set up will be completed later */
  60.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
  61. };
  62.  
  63. static struct idescriptor idt[IDT_ITEMS];
  64.  
  65. static struct tss tss;
  66.  
  67. struct tss *tss_p = NULL;
  68.  
  69. /* gdtr is changed by kmp before next CPU is initialized */
  70. struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
  71. struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) };
  72.  
  73. void gdt_setbase(struct descriptor *d, __address base)
  74. {
  75.     d->base_0_15 = base & 0xffff;
  76.     d->base_16_23 = ((base) >> 16) & 0xff;
  77.     d->base_24_31 = ((base) >> 24) & 0xff;
  78. }
  79.  
  80. void gdt_setlimit(struct descriptor *d, __u32 limit)
  81. {
  82.     d->limit_0_15 = limit & 0xffff;
  83.     d->limit_16_19 = (limit >> 16) & 0xf;
  84. }
  85.  
  86. void idt_setoffset(struct idescriptor *d, __address offset)
  87. {
  88.     /*
  89.      * Offset is a linear address.
  90.      */
  91.     d->offset_0_15 = offset & 0xffff;
  92.     d->offset_16_31 = offset >> 16;
  93. }
  94.  
  95. void tss_initialize(struct tss *t)
  96. {
  97.     memsetb((__address) t, sizeof(struct tss), 0);
  98. }
  99.  
  100. /*
  101.  * This function takes care of proper setup of IDT and IDTR.
  102.  */
  103. void idt_init(void)
  104. {
  105.     struct idescriptor *d;
  106.     int i;
  107.  
  108.     for (i = 0; i < IDT_ITEMS; i++) {
  109.         d = &idt[i];
  110.  
  111.         d->unused = 0;
  112.         d->selector = selector(KTEXT_DES);
  113.  
  114.         d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
  115.  
  116.         if (i == VECTOR_SYSCALL) {
  117.             /*
  118.              * The syscall interrupt gate must be calleable from userland.
  119.              */
  120.             d->access |= DPL_USER;
  121.         }
  122.        
  123.         idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
  124.         trap_register(i, null_interrupt);
  125.     }
  126.     trap_register(13, gp_fault);
  127.     trap_register( 7, nm_fault);
  128.     trap_register(12, ss_fault);
  129. }
  130.  
  131.  
  132. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  133. static void clean_IOPL_NT_flags(void)
  134. {
  135.     asm
  136.     (
  137.         "pushfl;"
  138.         "pop %%eax;"
  139.         "and $0xffff8fff,%%eax;"
  140.         "push %%eax;"
  141.         "popfl;"
  142.         :
  143.         :
  144.         :"%eax"
  145.     );
  146. }
  147.  
  148. /* Clean AM(18) flag in CR0 register */
  149. static void clean_AM_flag(void)
  150. {
  151.     asm
  152.     (
  153.         "mov %%cr0,%%eax;"
  154.         "and $0xFFFBFFFF,%%eax;"
  155.         "mov %%eax,%%cr0;"
  156.         :
  157.         :
  158.         :"%eax"
  159.     );
  160. }
  161.  
  162. void pm_init(void)
  163. {
  164.     struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base);
  165.  
  166.     /*
  167.      * Each CPU has its private GDT and TSS.
  168.      * All CPUs share one IDT.
  169.      */
  170.  
  171.     if (config.cpu_active == 1) {
  172.         idt_init();
  173.         /*
  174.          * NOTE: bootstrap CPU has statically allocated TSS, because
  175.          * the heap hasn't been initialized so far.
  176.          */
  177.         tss_p = &tss;
  178.     }
  179.     else {
  180.         tss_p = (struct tss *) malloc(sizeof(struct tss));
  181.         if (!tss_p)
  182.             panic("could not allocate TSS\n");
  183.     }
  184.  
  185.     tss_initialize(tss_p);
  186.    
  187.     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
  188.     gdt_p[TSS_DES].special = 1;
  189.     gdt_p[TSS_DES].granularity = 1;
  190.    
  191.     gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
  192.     gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
  193.  
  194.     /*
  195.      * As of this moment, the current CPU has its own GDT pointing
  196.      * to its own TSS. We just need to load the TR register.
  197.      */
  198.     __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
  199.    
  200.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
  201.     clean_AM_flag();          /* Disable alignment check */
  202. }
  203.