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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup amd64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch.h>
  36.  
  37. #include <arch/types.h>
  38.  
  39. #include <config.h>
  40.  
  41. #include <proc/thread.h>
  42. #include <arch/drivers/ega.h>
  43. #include <arch/drivers/vesa.h>
  44. #include <genarch/i8042/i8042.h>
  45. #include <arch/drivers/i8254.h>
  46. #include <arch/drivers/i8259.h>
  47.  
  48. #include <arch/bios/bios.h>
  49. #include <arch/mm/memory_init.h>
  50. #include <arch/cpu.h>
  51. #include <print.h>
  52. #include <arch/cpuid.h>
  53. #include <genarch/acpi/acpi.h>
  54. #include <panic.h>
  55. #include <interrupt.h>
  56. #include <arch/syscall.h>
  57. #include <arch/debugger.h>
  58. #include <syscall/syscall.h>
  59. #include <console/console.h>
  60.  
  61.  
  62. /** Disable I/O on non-privileged levels
  63.  *
  64.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  65.  */
  66. static void clean_IOPL_NT_flags(void)
  67. {
  68.     asm
  69.     (
  70.         "pushfq;"
  71.         "pop %%rax;"
  72.         "and $~(0x7000),%%rax;"
  73.         "pushq %%rax;"
  74.         "popfq;"
  75.         :
  76.         :
  77.         :"%rax"
  78.     );
  79. }
  80.  
  81. /** Disable alignment check
  82.  *
  83.  * Clean AM(18) flag in CR0 register
  84.  */
  85. static void clean_AM_flag(void)
  86. {
  87.     asm
  88.     (
  89.         "mov %%cr0,%%rax;"
  90.         "and $~(0x40000),%%rax;"
  91.         "mov %%rax,%%cr0;"
  92.         :
  93.         :
  94.         :"%rax"
  95.     );
  96. }
  97.  
  98. void arch_pre_mm_init(void)
  99. {
  100.     struct cpu_info cpuid_s;
  101.  
  102.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  103.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  104.         panic("Processor does not support No-execute pages.\n");
  105.  
  106.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  107.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  108.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  109.    
  110.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  111.         panic("Processor does not support SSE2 instructions.\n");
  112.  
  113.     /* Enable No-execute pages */
  114.     set_efer_flag(AMD_NXE_FLAG);
  115.     /* Enable FPU */
  116.     cpu_setup_fpu();
  117.  
  118.     /* Initialize segmentation */
  119.     pm_init();
  120.  
  121.         /* Disable I/O on nonprivileged levels
  122.      * clear the NT(nested-thread) flag
  123.      */
  124.     clean_IOPL_NT_flags();
  125.     /* Disable alignment check */
  126.     clean_AM_flag();
  127.  
  128.     if (config.cpu_active == 1) {
  129.         bios_init();
  130.         i8259_init();   /* PIC */
  131.         i8254_init();   /* hard clock */
  132.  
  133.         #ifdef CONFIG_SMP
  134.         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
  135.                  tlb_shootdown_ipi);
  136.         #endif /* CONFIG_SMP */
  137.     }
  138. }
  139.  
  140. void arch_post_mm_init(void)
  141. {
  142.     if (config.cpu_active == 1) {
  143. #ifdef CONFIG_FB
  144.         if (vesa_present())
  145.             vesa_init();
  146.         else
  147. #endif
  148.             ega_init(); /* video */
  149.         /* Enable debugger */
  150.         debugger_init();
  151.         /* Merge all memory zones to 1 big zone */
  152.         zone_merge_all();
  153.     }
  154.     /* Setup fast SYSCALL/SYSRET */
  155.     syscall_setup_cpu();
  156.    
  157. }
  158.  
  159. void arch_pre_smp_init(void)
  160. {
  161.     if (config.cpu_active == 1) {
  162.         memory_print_map();
  163.        
  164.         #ifdef CONFIG_SMP
  165.         acpi_init();
  166.         #endif /* CONFIG_SMP */
  167.     }
  168. }
  169.  
  170. void arch_post_smp_init(void)
  171. {
  172.     i8042_init();   /* keyboard controller */
  173. }
  174.  
  175. void calibrate_delay_loop(void)
  176. {
  177.     i8254_calibrate_delay_loop();
  178.     i8254_normal_operation();
  179. }
  180.  
  181. /** Set thread-local-storage pointer
  182.  *
  183.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  184.  * part can be set only in CPL0 mode.
  185.  *
  186.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  187.  * we need not to go to CPL0 to read it.
  188.  */
  189. unative_t sys_tls_set(unative_t addr)
  190. {
  191.     THREAD->arch.tls = addr;
  192.     write_msr(AMD_MSR_FS, addr);
  193.     return 0;
  194. }
  195.  
  196. /** Acquire console back for kernel
  197.  *
  198.  */
  199. void arch_grab_console(void)
  200. {
  201.     i8042_grab();
  202. }
  203. /** Return console to userspace
  204.  *
  205.  */
  206. void arch_release_console(void)
  207. {
  208.     i8042_release();
  209. }
  210.  
  211.  /** @}
  212.  */
  213.  
  214.