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  1. /*
  2.  * Copyright (c) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup mips32mm   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_mips32_PAGE_H_
  36. #define KERN_mips32_PAGE_H_
  37.  
  38. #include <arch/mm/frame.h>
  39.  
  40. #define PAGE_WIDTH  FRAME_WIDTH
  41. #define PAGE_SIZE   FRAME_SIZE
  42.  
  43. #define PAGE_COLOR_BITS 0           /* dummy */
  44.  
  45. #ifndef __ASM__
  46. #   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
  47. #   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
  48. #else
  49. #   define KA2PA(x) ((x) - 0x80000000)
  50. #   define PA2KA(x) ((x) + 0x80000000)
  51. #endif
  52.  
  53. #ifdef KERNEL
  54.  
  55. /*
  56.  * Implementation of generic 4-level page table interface.
  57.  *
  58.  * Page table layout:
  59.  * - 32-bit virtual addresses
  60.  * - Offset is 14 bits => pages are 16K long
  61.  * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
  62.  *   4 bytes long
  63.  * - PTE's replace EntryLo v (valid) bit with p (present) bit
  64.  * - PTE's use only one bit to distinguish between cacheable and uncacheable
  65.  *   mappings
  66.  * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
  67.  *   the p bit is cleared
  68.  * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
  69.  *   and bit A (accessed)
  70.  * - PTL0 has 64 entries (6 bits)
  71.  * - PTL1 is not used
  72.  * - PTL2 is not used
  73.  * - PTL3 has 4096 entries (12 bits)
  74.  */
  75.  
  76. /* Macros describing number of entries in each level. */
  77. #define PTL0_ENTRIES_ARCH   64
  78. #define PTL1_ENTRIES_ARCH   0
  79. #define PTL2_ENTRIES_ARCH   0
  80. #define PTL3_ENTRIES_ARCH   4096
  81.  
  82. /* Macros describing size of page tables in each level. */
  83. #define PTL0_SIZE_ARCH      ONE_FRAME
  84. #define PTL1_SIZE_ARCH      0
  85. #define PTL2_SIZE_ARCH      0
  86. #define PTL3_SIZE_ARCH      ONE_FRAME
  87.  
  88. /* Macros calculating entry indices for each level. */
  89. #define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
  90. #define PTL1_INDEX_ARCH(vaddr)  0
  91. #define PTL2_INDEX_ARCH(vaddr)  0
  92. #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
  93.  
  94. /* Set accessor for PTL0 address. */
  95. #define SET_PTL0_ADDRESS_ARCH(ptl0)
  96.  
  97. /* Get PTE address accessors for each level. */
  98. #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
  99.     (((pte_t *) (ptl0))[(i)].pfn << 12)
  100. #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
  101.     (ptl1)
  102. #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
  103.     (ptl2)
  104. #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
  105.     (((pte_t *) (ptl3))[(i)].pfn << 12)
  106.  
  107. /* Set PTE address accessors for each level. */
  108. #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
  109.     (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
  110. #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
  111. #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
  112. #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
  113.     (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
  114.  
  115. /* Get PTE flags accessors for each level. */
  116. #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
  117.     get_pt_flags((pte_t *) (ptl0), (index_t) (i))
  118. #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
  119.     PAGE_PRESENT
  120. #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
  121.     PAGE_PRESENT
  122. #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
  123.     get_pt_flags((pte_t *) (ptl3), (index_t) (i))
  124.  
  125. /* Set PTE flags accessors for each level. */
  126. #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
  127.     set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
  128. #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
  129. #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
  130. #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
  131.     set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
  132.  
  133. /* Last-level info macros. */
  134. #define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
  135. #define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
  136. #define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
  137. #define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
  138. #define PTE_EXECUTABLE_ARCH(pte)        1
  139.  
  140. #ifndef __ASM__
  141.  
  142. #include <mm/mm.h>
  143. #include <arch/exception.h>
  144.  
  145. static inline int get_pt_flags(pte_t *pt, index_t i)
  146. {
  147.     pte_t *p = &pt[i];
  148.    
  149.     return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
  150.         ((!p->p) << PAGE_PRESENT_SHIFT) |
  151.         (1 << PAGE_USER_SHIFT) |
  152.         (1 << PAGE_READ_SHIFT) |
  153.         ((p->w) << PAGE_WRITE_SHIFT) |
  154.         (1 << PAGE_EXEC_SHIFT) |
  155.         (p->g << PAGE_GLOBAL_SHIFT));
  156. }
  157.  
  158. static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
  159. {
  160.     pte_t *p = &pt[i];
  161.    
  162.     p->cacheable = (flags & PAGE_CACHEABLE) != 0;
  163.     p->p = !(flags & PAGE_NOT_PRESENT);
  164.     p->g = (flags & PAGE_GLOBAL) != 0;
  165.     p->w = (flags & PAGE_WRITE) != 0;
  166.    
  167.     /*
  168.      * Ensure that valid entries have at least one bit set.
  169.      */
  170.     p->soft_valid = 1;
  171. }
  172.  
  173. extern void page_arch_init(void);
  174.  
  175. #endif /* __ASM__ */
  176.  
  177. #endif /* KERNEL */
  178.  
  179. #endif
  180.  
  181. /** @}
  182.  */
  183.