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  1. /*
  2.  * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32mm
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34. #include <panic.h>
  35. #include <arch/exception.h>
  36. #include <arch/debug_print/print.h>
  37. #include <arch/mm/page_fault.h>
  38. #include <mm/as.h>
  39. #include <genarch/mm/page_pt.h>
  40. #include <arch.h>
  41. #include <interrupt.h>
  42.  
  43.  
  44. //TODO: remove in final version
  45. static void print_istate(istate_t* istate);
  46. static void print_istate(istate_t* istate) {
  47.  dprintf("\nIstate dump:\n");
  48.  dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
  49.  dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
  50.  dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
  51.  dprintf("   r12:%X    sp:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
  52. }
  53.  
  54. /**
  55.  * \return Value stored in fault status register
  56.  */
  57. static inline fault_status_t read_fault_status_register() {
  58.         fault_status_union_t tmp;
  59.         asm volatile (
  60.         "mrc p15, 0, %0, c5, c0, 0"
  61.             : "=r"(tmp.dummy)
  62.     );
  63.     return tmp.fsr;
  64. }
  65.  
  66. /**
  67.  * \return Virtual adress. Access on this addres caused exception
  68.  */
  69. static inline uintptr_t read_fault_address_register() {
  70.         uintptr_t tmp;
  71.     // Fault adress is stored in coprocessor15, register 6
  72.     asm volatile (
  73.         "mrc p15, 0, %0, c6, c0, 0"
  74.         : "=r"(tmp)
  75.     );
  76.     return tmp;
  77. };
  78.  
  79. /** Check type of instruction
  80.  * \param i_code Instruction op code
  81.  * \return true if instruction is load or store, false otherwise
  82.  */
  83. static inline bool load_store_instruction(instruction_t i_code) {
  84.  
  85.      // load store immediate offset
  86.     if (i_code.instr_type == 0x2) {
  87.         return true;
  88.     };
  89.  
  90.         // load store register offset
  91.         if (i_code.instr_type == 0x3 && i_code.bit4 == 0) {
  92.         return true;
  93.     };
  94.  
  95.         // load store multiple
  96.         if (i_code.instr_type == 0x4) {
  97.         return true;
  98.     };
  99.  
  100.         // coprocessor load / strore
  101.     if (i_code.instr_type == 0x6) {
  102.         return true;
  103.     };
  104.  
  105.     return false;
  106. }
  107.  
  108. /** Check type of instruction
  109.  * \param i_code Instruction op code
  110.  * \return true if instruction is swap, false otherwise
  111.  */
  112. static inline bool swap_instruction(instruction_t i_code) {
  113.  
  114.     // swap, swapb instruction
  115.     if (i_code.instr_type == 0x0 &&
  116.         (i_code.opcode == 0x8 || i_code.opcode == 0xA) &&
  117.         i_code.access == 0x0 && i_code.bits567 == 0x4 &&
  118.         i_code.bit4 == 1) {
  119.         return true;
  120.     };
  121.  
  122.     return false;
  123. }
  124.  
  125.  
  126. /**
  127.  * Decode instruction and decide if try to read or write into memmory.
  128.  *
  129.  * \param instr_addr address of instruction which attempts access into memmory
  130.  * \param badvaddr Virtual address on which instruction tries to access
  131.  * \return type of access into memmory
  132.  *  Note: return PF_ACESS_EXEC if no memmory acess
  133.  */
  134. //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC
  135. static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) {
  136.         instruction_union_t tmp;
  137.         tmp.ip = instr_addr;
  138.     // get instruction op code
  139.     instruction_t i_code = *(tmp.instr);
  140.  
  141. //         dprintf("get_instruction_memmory_access\n");
  142. //  dprintf(" instr_addr:%X\n",instr_addr);
  143. //  dprintf(" i_code:%X\n",i_code);
  144. //  dprintf(" i_code.condition:%d\n", i_code.condition);
  145. //  dprintf(" i_code.instr_type:%d\n",i_code.instr_type);
  146. //  dprintf(" i_code.opcode:%d\n",i_code.opcode);
  147. //  dprintf(" i_code.acess:%d\n", i_code.access);
  148. //  dprintf(" i_code.dummy:%d\n", i_code.dummy);
  149. //  dprintf(" i_code.bits567%d\n", i_code.bits567);
  150. //  dprintf(" i_code.bit4:%d\n", i_code.bit4);
  151. //  dprintf(" i_code.dummy1:%d\n", i_code.dummy1);
  152.  
  153.  
  154.         // undefined instructions ... (or special instructions)
  155.     if (i_code.condition == 0xf) {
  156.         panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
  157.         return PF_ACCESS_EXEC;
  158.     };
  159.  
  160.     // load store instructions
  161.         if (load_store_instruction(i_code)) {
  162.         if ( i_code.access == 1) {
  163.             return PF_ACCESS_READ;
  164.         } else {
  165.             return PF_ACCESS_WRITE;
  166.         }
  167.     };
  168.  
  169.     // swap, swpb instruction
  170.     if (swap_instruction(i_code))
  171.      {
  172.         /* Swap instructions make read and write in one step.
  173.          * Type of access that caused exception have to page tables
  174.          *  and access rights.
  175.          */
  176. //TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread
  177. //      but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data
  178. //  same case as_page_fault .... it's nessesary to solve "stack" problem
  179.                 pte_level1_t* pte = (pte_level1_t*)
  180.             pt_mapping_operations.mapping_find(AS, badvaddr);
  181.  
  182.         ASSERT(pte);
  183.  
  184.                 /* check if read possible
  185.                  * Note: Don't check PTE_READABLE because it returns 1 everytimes */
  186.         if ( !PTE_PRESENT(pte) ) {
  187.                 return PF_ACCESS_READ;
  188.         }
  189.         if ( !PTE_WRITABLE(pte) ) {
  190.             return PF_ACCESS_WRITE;
  191.         }
  192.         else
  193.             // badvaddr is present readable and writeable but error occured ... why?
  194.             panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
  195.     }
  196.     panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
  197.     return PF_ACCESS_EXEC;
  198. }
  199.  
  200. /**
  201.  * Routine that solves exception data_abourt
  202.  *  ... you try to load or store value into invalid memmory address
  203.  * \param istate State of CPU when data abourt occured
  204.  * \param n number of exception
  205.  */
  206. //TODO: remove debug prints in final tested version
  207. void data_abort(int n, istate_t *istate) {
  208.         fault_status_t fsr = read_fault_status_register();
  209.         uintptr_t  page = read_fault_address_register();
  210.  
  211.     pf_access_t access = get_memmory_access_type( istate->lr, page);
  212.  
  213. //  print_istate(istate);
  214.     dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->lr, page, fsr.status,fsr, access);
  215.  
  216. /* Alf: Will be commented until stack problem will be solved ...
  217.     as_page_fault make consequent page faults*/
  218.  
  219.         int ret = as_page_fault(page, access, istate);
  220.     dprintf(" as_page_fault ret:%d\n", ret);
  221.         if (ret == AS_PF_FAULT) {
  222.         fault_if_from_uspace(istate, "Page fault: %#x", page);
  223.  
  224.                 panic("page fault\n");
  225.         }
  226.  
  227.     // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures
  228.     panic("page fault ... solved\n");
  229.  
  230. }
  231.  
  232. /**
  233.  * Routine that solves exception prefetch_about
  234.  *  ... you try to execute instruction on invalid address
  235.  * \param istate State of CPU when prefetch abourt occured
  236.  * \param n number of exception
  237.  */
  238. void prefetch_abort(int n, istate_t *istate) {
  239.  // Prefetch can be made be bkpt instruction
  240.     print_istate(istate);
  241.     dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->lr);
  242.  
  243. /* Alf: Will be commented until stack problem will be solved ...
  244.     as_page_fault make consequent page faults*/
  245.  
  246.     int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate);
  247.     dprintf(" as_page_fault ret:%d\n", ret);
  248.         if (ret == AS_PF_FAULT) {
  249.                 panic("page fault - instruction fetch at addr:%X\n", istate->lr);
  250.         }
  251.  
  252.  
  253.     panic("Prefetch abourt ... solved");
  254. }
  255.  
  256. /** @}
  257.  */
  258.  
  259.