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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Interrupts controlling routines.
  34.  */
  35.  
  36. #include <arch/asm.h>
  37. #include <arch/regutils.h>
  38. #include <ddi/irq.h>
  39. #include <arch/machine.h>
  40. #include <interrupt.h>
  41.  
  42. /** Initial size of a table holding interrupt handlers. */
  43. #define IRQ_COUNT 8
  44.  
  45.  
  46. /** Disable interrupts.
  47.  *
  48.  * @return Old interrupt priority level.
  49.  */
  50. ipl_t interrupts_disable(void)
  51. {
  52.     ipl_t ipl = current_status_reg_read();
  53.  
  54.     current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
  55.    
  56.     return ipl;
  57. }
  58.  
  59.  
  60. /** Enable interrupts.
  61.  *
  62.  * @return Old interrupt priority level.
  63.  */
  64. ipl_t interrupts_enable(void)
  65. {
  66.     ipl_t ipl = current_status_reg_read();
  67.  
  68.     current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
  69.  
  70.     return ipl;
  71. }
  72.  
  73.  
  74. /** Restore interrupt priority level.
  75.  *
  76.  * @param ipl Saved interrupt priority level.
  77.  */
  78. void interrupts_restore(ipl_t ipl)
  79. {
  80.     current_status_reg_control_write(
  81.         (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
  82.         (ipl & STATUS_REG_IRQ_DISABLED_BIT)
  83.     );
  84. }
  85.  
  86.  
  87. /** Read interrupt priority level.
  88.  *
  89.  * @return Current interrupt priority level.
  90.  */
  91. ipl_t interrupts_read(void)
  92. {
  93.     return current_status_reg_read();
  94. }
  95.  
  96.  
  97. /** Initialize basic tables for exception dispatching
  98.  * and starts the timer.
  99.  */
  100. void interrupt_init(void)
  101. {
  102.     irq_init(IRQ_COUNT, IRQ_COUNT);
  103.     machine_timer_irq_start();
  104. }
  105.  
  106.  
  107. /** @}
  108.  */
  109.