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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.     @brief  Exception handlers and exception initialization routines.
  34.  */
  35.  
  36. #include <arch/exception.h>
  37. #include <arch/debug_print/print.h>
  38. #include <arch/memstr.h>
  39. #include <arch/regutils.h>
  40. #include <interrupt.h>
  41. #include <arch/drivers/gxemul.h>
  42. #include <arch/mm/page_fault.h>
  43. #include <print.h>
  44. #include <syscall/syscall.h>
  45.  
  46. #define PREFETCH_OFFSET     0x8
  47. #define BRANCH_OPCODE       0xea000000
  48. #define LDR_OPCODE      0xe59ff000
  49. #define VALID_BRANCH_MASK   0xff000000
  50. #define EXC_VECTORS_SIZE    0x20
  51. #define EXC_VECTORS     0x8
  52.  
  53. extern uintptr_t supervisor_sp;
  54. extern uintptr_t exc_stack;
  55.  
  56. inline static void setup_stack_and_save_regs()
  57. {
  58. asm volatile(   "ldr r13, =exc_stack        \n\
  59.     stmfd r13!, {r0}            \n\
  60.     mrs r0, spsr                \n\
  61.     and r0, r0, #0x1f           \n\
  62.     cmp r0, #0x10               \n\
  63.     bne 1f                  \n\
  64.                         \n\
  65.     @prev mode was usermode         \n\
  66.     ldmfd r13!, {r0}            \n\
  67.     ldr r13, =supervisor_sp         \n\
  68.     stmfd r13!, {lr}            \n\
  69.     stmfd r13!, {r0-r12}            \n\
  70.     stmfd r13!, {r13, lr}^          \n\
  71.     mrs r0, spsr                \n\
  72.     stmfd r13!, {r0}            \n\
  73.     b 2f                    \n\
  74.                         \n\
  75.     @prev mode was not usermode     \n\
  76. 1:                      \n\
  77.     stmfd r13!, {r1, r2, r3}        \n\
  78.     mrs r1, cpsr                \n\
  79.     mov r2, lr              \n\
  80.     bic r1, r1, #0x1f           \n\
  81.     orr r1, r1, r0              \n\
  82.     mrs r0, cpsr                \n\
  83.     msr cpsr_c, r1              \n\
  84.                         \n\
  85.     mov r3, r13             \n\
  86.     stmfd r13!, {r2}            \n\
  87.     mov r2, lr              \n\
  88.     stmfd r13!, {r4-r12}            \n\
  89.     mov r1, r13             \n\
  90.     mov lr, #0              \n\
  91.     mov sp, #0              \n\
  92.     msr cpsr_c, r0              \n\
  93.                         \n\
  94.     ldmfd r13!, {r4, r5, r6, r7}        \n\
  95.     stmfd r1!, {r4, r5, r6}         \n\
  96.     stmfd r1!, {r7}             \n\
  97.     stmfd r1!, {r2}             \n\
  98.     stmfd r1!, {r3}             \n\
  99.     mrs r0, spsr                \n\
  100.     stmfd r1!, {r0}             \n\
  101.     mov r13, r1             \n\
  102. 2:"
  103. );
  104. }
  105.  
  106.  
  107. inline static void load_regs()
  108. {
  109. asm volatile(   "ldmfd r13!, {r0}       \n\
  110.     msr spsr, r0                \n\
  111.     and r0, r0, #0x1f           \n\
  112.     cmp r0, #0x10               \n\
  113.     bne 3f                  \n\
  114.                         \n\
  115.     @return to user mode            \n\
  116.     ldmfd r13!, {r13, lr}^          \n\
  117.     b 4f                    \n\
  118.                         \n\
  119.     @return to non-user mode        \n\
  120. 3:                      \n\
  121.     ldmfd r13!, {r1, r2}            \n\
  122.     mrs r3, cpsr                \n\
  123.     bic r3, r3, #0x1f           \n\
  124.     orr r3, r3, r0              \n\
  125.     mrs r0, cpsr                \n\
  126.     msr cpsr_c, r3              \n\
  127.                         \n\
  128.     mov r13, r1             \n\
  129.     mov lr, r2              \n\
  130.     msr cpsr_c, r0              \n\
  131.                         \n\
  132.     @actual return              \n\
  133.                         \n\
  134.     ldmfd r13, {r0-r12, pc}^        \n\
  135. 4:"
  136. );
  137. }
  138.  
  139.  
  140.  
  141. /*#define SAVE_REGS_TO_STACK            \
  142.     asm("stmfd r13!, {r0-r12, r13, lr}");   \
  143.     asm("mrs r14, spsr");           \
  144.     asm("stmfd r13!, {r14}");
  145. */
  146.  
  147.  
  148. #define CALL_EXC_DISPATCH(exception)        \
  149.     asm("mov r0, %0" : : "i" (exception));  \
  150.     asm("mov r1, r13");         \
  151.     asm("bl exc_dispatch");    
  152.  
  153.  
  154. /**Loads registers from the stack and resets SPSR before exitting exception
  155.  * handler.
  156.  
  157. #define LOAD_REGS_FROM_STACK            \
  158.     asm("ldmfd r13!, {r14}");       \
  159.     asm("msr spsr, r14");           \
  160.     asm("ldmfd r13!, {r0-r12, r13, pc}^");
  161.  */
  162.  
  163.    
  164. /** General exception handler.
  165.  *  Stores registers, dispatches the exception,
  166.  *  and finally restores registers and returns from exception processing.
  167.  */
  168.  
  169. #define PROCESS_EXCEPTION(exception)        \
  170.     setup_stack_and_save_regs();        \
  171.     CALL_EXC_DISPATCH(exception)        \
  172.     load_regs();
  173.  
  174. /* #define PROCESS_EXCEPTION(exception)     \
  175.     SAVE_REGS_TO_STACK      \
  176.     CALL_EXC_DISPATCH(exception)        \
  177.     LOAD_REGS_FROM_STACK*/
  178.  
  179. /** Updates specified exception vector to jump to given handler.
  180.  * Addresses of handlers are stored in memory following exception vectors.
  181.  */
  182. static void install_handler (unsigned handler_addr, unsigned* vector)
  183. {
  184.     /* relative address (related to exc. vector) of the word
  185.      * where handler's address is stored
  186.     */
  187.     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
  188.    
  189.     /* make it LDR instruction and store at exception vector */
  190.     *vector = handler_address_ptr | LDR_OPCODE;
  191.    
  192.     /* store handler's address */
  193.     *(vector + EXC_VECTORS) = handler_addr;
  194.  
  195. }
  196.  
  197.  
  198. static void reset_exception_entry()
  199. {
  200.     PROCESS_EXCEPTION(EXC_RESET);
  201. }
  202.  
  203. /** Low-level Software Interrupt Exception handler */
  204. static void swi_exception_entry()
  205. {
  206.     PROCESS_EXCEPTION(EXC_SWI);
  207. }
  208.  
  209. /** Low-level Undefined Instruction Exception handler */
  210. static void undef_instr_exception_entry()
  211. {
  212.     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
  213. }
  214.  
  215. /** Low-level Fast Interrupt Exception handler */
  216. static void fiq_exception_entry()
  217. {
  218.     PROCESS_EXCEPTION(EXC_FIQ);
  219. }
  220.  
  221. /** Low-level Prefetch Abort Exception handler */
  222. static void prefetch_abort_exception_entry()
  223. {
  224.     asm("sub lr, lr, #4");
  225.     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
  226. }
  227.  
  228. /** Low-level Data Abort Exception handler */
  229. static void data_abort_exception_entry()
  230. {
  231.     asm("sub lr, lr, #8");
  232.     PROCESS_EXCEPTION(EXC_DATA_ABORT);
  233. }
  234.  
  235.  
  236. /** Low-level Interrupt Exception handler */
  237. static void irq_exception_entry()
  238. {
  239.     asm("sub lr, lr, #4");
  240.     PROCESS_EXCEPTION(EXC_IRQ);
  241. }
  242.  
  243. /** Software Interrupt handler.
  244.  *
  245.  * Dispatches the syscall.
  246.  */
  247. static void swi_exception(int exc_no, istate_t* istate)
  248. {
  249.     istate->r0 = syscall_handler(
  250.         istate->r0,
  251.         istate->r1,
  252.         istate->r2,
  253.         istate->r3,
  254.         istate->r4);
  255. }
  256.  
  257. /** Interrupt Exception handler.
  258.  *
  259.  * Determines the sources of interrupt, and calls their handlers.
  260.  */
  261. static void irq_exception(int exc_no, istate_t* istate)
  262. {
  263. // TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar
  264. // name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM
  265. #if MACHINE == MACHINE_GXEMUL_TESTARM
  266.     uint32_t sources = gxemul_irqc_get_sources();
  267.     int i = 0;
  268.     for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {
  269.         if (sources & (1 << i)) {
  270.             irq_t *irq = irq_dispatch_and_lock(i);
  271.             if (irq) {
  272.                 /* The IRQ handler was found. */
  273.                 irq->handler(irq, irq->arg);
  274.                 spinlock_unlock(&irq->lock);
  275.             } else {
  276.                 /* Spurious interrupt.*/
  277.                 dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);
  278.             }
  279.         }
  280.     }
  281. #endif
  282. /* TODO remove after testing the above code
  283.             noirq = 0;
  284.             if (i == CONSOLE_IRQ) {
  285.                 char readchar = *(char*)0x10000000;
  286.                 if (readchar == 0) {
  287.                     aux_puts("?");
  288.                 }
  289.                 else {
  290.                     dprintf("%c", readchar);
  291.                 }
  292.                
  293.             }
  294.             else if (i == TIMER_IRQ) {
  295.                 dprintf("\n.\n");
  296.                 //acknowledge
  297.                 *(uint32_t*)0x15000110 = 0;
  298.             }
  299.         }
  300.     }
  301.  
  302.     if (noirq)
  303.     aux_puts("IRQ exception without source\n");*/
  304. }
  305.  
  306. /** Fills exception vectors with appropriate exception handlers.
  307. */
  308. void install_exception_handlers(void)
  309. {
  310.     install_handler((unsigned)reset_exception_entry,
  311.              (unsigned*)EXC_RESET_VEC);
  312.    
  313.     install_handler((unsigned)undef_instr_exception_entry,
  314.              (unsigned*)EXC_UNDEF_INSTR_VEC);
  315.    
  316.     install_handler((unsigned)swi_exception_entry,
  317.              (unsigned*)EXC_SWI_VEC);
  318.    
  319.     install_handler((unsigned)prefetch_abort_exception_entry,
  320.              (unsigned*)EXC_PREFETCH_ABORT_VEC);
  321.    
  322.     install_handler((unsigned)data_abort_exception_entry,
  323.              (unsigned*)EXC_DATA_ABORT_VEC);
  324.    
  325.     install_handler((unsigned)irq_exception_entry,
  326.              (unsigned*)EXC_IRQ_VEC);
  327.    
  328.     install_handler((unsigned)fiq_exception_entry,
  329.              (unsigned*)EXC_FIQ_VEC);
  330. }
  331.  
  332. #ifdef HIGH_EXCEPTION_VECTORS
  333. /** Activates using high exception vectors addresses. */
  334.  static void high_vectors()
  335. {
  336.     uint32_t control_reg;
  337.    
  338.     asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
  339.    
  340.     //switch on the high vectors bit
  341.     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
  342.    
  343.     asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
  344. }
  345. #endif
  346.  
  347. /** Initializes exception handling.
  348.  *
  349.  * Installs low-level exception handlers and then registers
  350.  * exceptions and their handlers to kernel exception dispatcher.
  351.  */
  352. void exception_init(void)
  353. {
  354. #ifdef HIGH_EXCEPTION_VECTORS
  355.     high_vectors();
  356. #endif
  357.     install_exception_handlers();
  358.    
  359.     exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
  360.     exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
  361.     exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
  362.     exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
  363.     /* TODO add next */
  364. }
  365.  
  366. /** Sets stack pointers in all supported exception modes.
  367.  *
  368.  * @param stack_ptr stack pointer
  369.  */
  370. void setup_exception_stacks()
  371. {
  372.         /* switch to particular mode and set "r13" there */
  373.  
  374.         uint32_t cspr = current_status_reg_read();
  375.  
  376.         /* IRQ stack */
  377.         current_status_reg_control_write(
  378.                         (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE
  379.         );
  380.         asm("ldr r13, =exc_stack");
  381.  
  382.         /* abort stack */
  383.         current_status_reg_control_write(
  384.                         (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE
  385.         );
  386.         asm("ldr r13, =exc_stack");
  387.  
  388.         /* TODO if you want to test other exceptions than IRQ,
  389.         make stack analogous to irq_stack (in start.S),
  390.         and then set stack pointer here */
  391.  
  392.         current_status_reg_control_write(cspr);
  393.  
  394. }
  395.  
  396. /** @}
  397.  */
  398.