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  1. /*
  2.  * Copyright (c) 2009 Vineeth Pillai
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32qemu_icp
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief QEMU icp drivers.
  34.  */
  35.  
  36. #include <interrupt.h>
  37. #include <ipc/irq.h>
  38. #include <console/chardev.h>
  39. #include <arch/drivers/qemu.h>
  40. #include <arch/drivers/pl050.h>
  41. #include <console/console.h>
  42. #include <sysinfo/sysinfo.h>
  43. #include <print.h>
  44. #include <ddi/device.h>
  45. #include <mm/page.h>
  46. #include <arch/machine.h>
  47. #include <arch/debug/print.h>
  48. #include <genarch/fb/fb.h>
  49. #include <genarch/fb/visuals.h>
  50.  
  51. /* Addresses of devices. */
  52. #define QEMU_ICP_VIDEORAM            0x16000000
  53. #define QEMU_ICP_KBD                 0x18000000
  54. #define ICP_KBD_STAT             0x04
  55. #define ICP_KBD_DATA             0x08
  56. #define ICP_KBD_INTR_STAT        0x10
  57. #define QEMU_ICP_HALT_OFFSET         0x10
  58. #define QEMU_ICP_RTC                 0x13000000
  59. #define QEMU_ICP_RTC1_LOAD_OFFSET    0x100
  60. #define QEMU_ICP_RTC1_READ_OFFSET    0x104
  61. #define QEMU_ICP_RTC1_CTL_OFFSET     0x108
  62. #define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C
  63. #define QEMU_ICP_RTC1_BGLOAD_OFFSET  0x118
  64. #define QEMU_ICP_RTC_CTL_VALUE       0x00E2
  65. #define QEMU_ICP_IRQC                0x14000000
  66. #define QEMU_ICP_IRQC_MASK_OFFSET    0xC
  67. #define QEMU_ICP_IRQC_UNMASK_OFFSET  0x8
  68. #define QEMU_ICP_MP                  0x11000000
  69. #define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
  70. #define QEMU_ICP_FB                  0x01000000
  71.  
  72. #define ICP_VGA              0xC0000000
  73. #define ICP_CMCR             0x10000000
  74.  
  75. /* IRQs */
  76. #define QEMU_ICP_KBD_IRQ        3
  77. #define QEMU_ICP_TIMER_IRQ      6
  78.  
  79. static qemu_icp_hw_map_t qemu_icp_hw_map;
  80. static irq_t qemu_icp_timer_irq;
  81.  
  82. static bool hw_map_init_called = false;
  83. static bool vga_init = false;
  84.  
  85. void icp_vga_init(void);
  86.  
  87. /** Initializes the vga
  88.  *
  89.  */
  90. void icp_vga_init(void)
  91. {
  92.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000;
  93.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000;
  94.     *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C;
  95.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF;
  96.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800;
  97.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB;
  98.     *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B;
  99.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000;
  100.    
  101. }
  102.  
  103. /** Returns the mask of active interrupts. */
  104. static inline uint32_t qemu_icp_irqc_get_sources(void)
  105. {
  106.     return *((uint32_t *) qemu_icp_hw_map.irqc);
  107. }
  108.  
  109.  
  110. /** Masks interrupt.
  111.  *
  112.  * @param irq interrupt number
  113.  */
  114. static inline void qemu_icp_irqc_mask(uint32_t irq)
  115. {
  116.     *((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq);
  117. }
  118.  
  119.  
  120. /** Unmasks interrupt.
  121.  *
  122.  * @param irq interrupt number
  123.  */
  124. static inline void qemu_icp_irqc_unmask(uint32_t irq)
  125. {
  126.     *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq);
  127. }
  128.  
  129. /** Initializes the icp frame buffer */
  130. void qemu_icp_fb_init(void)
  131. {
  132.     fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0);
  133. }
  134.  
  135. /** Initializes #qemu_icp_hw_map. */
  136. void qemu_icp_hw_map_init(void)
  137. {
  138.     qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
  139.     qemu_icp_hw_map.kbd_ctrl = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
  140.     qemu_icp_hw_map.kbd_stat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_STAT;
  141.     qemu_icp_hw_map.kbd_data = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_DATA;
  142.     qemu_icp_hw_map.kbd_intstat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
  143.     qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
  144.     qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET;
  145.     qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET;
  146.     qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET;
  147.     qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET;
  148.     qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET;
  149.  
  150.     qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
  151.     qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
  152.     qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
  153.         QEMU_ICP_IRQC_UNMASK_OFFSET;
  154.     qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
  155.     qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
  156.  
  157.     //icp_vga_init();
  158.  
  159.     hw_map_init_called = true;
  160. }
  161.  
  162.  
  163. /** Acquire console back for kernel. */
  164. void qemu_icp_grab_console(void)
  165. {
  166.     pl050_grab();
  167. }
  168.  
  169. /** Return console to userspace. */
  170. void qemu_icp_release_console(void)
  171. {
  172.     pl050_release();
  173. }
  174.  
  175. /** Initializes console object representing qemu_icp console.
  176.  *
  177.  *  @param devno device number.
  178.  */
  179. void qemu_icp_console_init(devno_t devno)
  180. {
  181.    
  182.     qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ);
  183.     pl050_init(devno, QEMU_ICP_KBD_IRQ, QEMU_ICP_KBD, qemu_icp_hw_map.kbd_ctrl);
  184.     qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ);
  185. }
  186.  
  187. /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts.
  188.  *
  189.  * @param frequency Interrupts frequency (0 disables RTC).
  190.  */
  191. static void qemu_icp_timer_start(uint32_t frequency)
  192. {
  193.     qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ);
  194.     *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency;
  195.     *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency;
  196.     *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE;
  197.     qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ);
  198. }
  199.  
  200. static irq_ownership_t qemu_icp_timer_claim(void)
  201. {
  202.     return IRQ_ACCEPT;
  203. }
  204.  
  205. /** Timer interrupt handler.
  206.  *
  207.  * @param irq Interrupt information.
  208.  * @param arg Not used.
  209.  */
  210. static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...)
  211. {
  212.     /*
  213.     * We are holding a lock which prevents preemption.
  214.     * Release the lock, call clock() and reacquire the lock again.
  215.     */
  216.     *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1;
  217.     spinlock_unlock(&irq->lock);
  218.     clock();
  219.     spinlock_lock(&irq->lock);
  220.  
  221. }
  222.  
  223. /** Initializes and registers timer interrupt handler. */
  224. static void qemu_icp_timer_irq_init(void)
  225. {
  226.     irq_initialize(&qemu_icp_timer_irq);
  227.     qemu_icp_timer_irq.devno = device_assign_devno();
  228.     qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ;
  229.     qemu_icp_timer_irq.claim = qemu_icp_timer_claim;
  230.     qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler;
  231.  
  232.     irq_register(&qemu_icp_timer_irq);
  233. }
  234.  
  235.  
  236. /** Starts timer.
  237.  *
  238.  * Initiates regular timer interrupts after initializing
  239.  * corresponding interrupt handler.
  240.  */
  241. void qemu_icp_timer_irq_start(void)
  242. {
  243.     qemu_icp_timer_irq_init();
  244.     qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ);
  245. }
  246.  
  247. /** Returns the size of emulated memory.
  248.  *
  249.  * @return Size in bytes.
  250.  */
  251. size_t qemu_icp_get_memory_size(void)
  252. {
  253.     //return  *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET));
  254.     return 0x2000000;
  255. }
  256.  
  257. /** Prints a character.
  258.  *
  259.  *  @param ch Character to be printed.
  260.  */
  261. void qemu_icp_debug_putc(char ch)
  262. {
  263.     char *addr = 0;
  264.     if (!hw_map_init_called) {
  265.         addr = (char *) QEMU_ICP_KBD;
  266.     } else {
  267.         addr = (char *) qemu_icp_hw_map.videoram;
  268.     }
  269.    
  270.     if (ch == '\n')
  271.         *(addr) = '\r';
  272.     *(addr) = ch;
  273. }
  274.  
  275. /** Stops qemu_icp. */
  276. void qemu_icp_cpu_halt(void)
  277. {
  278.     while (1);
  279. }
  280.  
  281. /** Gxemul specific interrupt exception handler.
  282.  *
  283.  * Determines sources of the interrupt from interrupt controller and
  284.  * calls high-level handlers for them.
  285.  *
  286.  * @param exc_no Interrupt exception number.
  287.  * @param istate Saved processor state.
  288.  */
  289. void qemu_icp_irq_exception(int exc_no, istate_t *istate)
  290. {
  291.     uint32_t sources = qemu_icp_irqc_get_sources();
  292.     int i;
  293.    
  294.     for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) {
  295.         if (sources & (1 << i)) {
  296.             irq_t *irq = irq_dispatch_and_lock(i);
  297.             if (irq) {
  298.                 /* The IRQ handler was found. */
  299.                 irq->handler(irq, irq->arg);
  300.                 spinlock_unlock(&irq->lock);
  301.             } else {
  302.                 /* Spurious interrupt.*/
  303.                 dprintf("cpu%d: spurious interrupt (inum=%d)\n",
  304.                     CPU->id, i);
  305.             }
  306.         }
  307.     }
  308. }
  309.  
  310. /** Returns address of framebuffer device.
  311.  *
  312.  *  @return Address of framebuffer device.
  313.  */
  314. uintptr_t qemu_icp_get_fb_address(void)
  315. {
  316.     if (!vga_init) {
  317.         icp_vga_init();
  318.         vga_init = true;
  319.     }
  320.     return (uintptr_t) QEMU_ICP_FB;
  321. }
  322.  
  323.  
  324. /** @}
  325.  */
  326.