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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32  
  30.  * @{
  31.  */
  32. /**
  33.  * @file
  34.  * @brief Utilities for convenient manipulation with ARM registers.
  35.  */
  36.  
  37. #ifndef KERN_arm32_REGUTILS_H_
  38. #define KERN_arm32_REGUTILS_H_
  39.  
  40.  
  41. #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
  42. #define STATUS_REG_MODE_MASK        0x1f
  43.  
  44. #define CP15_R1_HIGH_VECTORS_BIT    (1 << 13)
  45.  
  46.  
  47. /* ARM Processor Operation Modes */
  48. #define USER_MODE         0x10
  49. #define FIQ_MODE          0x11
  50. #define IRQ_MODE          0x12
  51. #define SUPERVISOR_MODE   0x13
  52. #define ABORT_MODE        0x17
  53. #define UNDEFINED_MODE    0x1b
  54. #define SYSTEM_MODE       0x1f
  55.  
  56.  
  57. /* [CS]PRS manipulation macros */
  58. #define GEN_STATUS_READ(nm,reg) \
  59.   static inline uint32_t nm## _status_reg_read(void) \
  60.   { \
  61.       uint32_t retval; \
  62.       asm volatile("mrs %0, " #reg : "=r"(retval)); \
  63.       return retval; \
  64.   }
  65.  
  66. #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
  67.   static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
  68.   { \
  69.       asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \
  70.   }
  71.  
  72.  
  73. /** Returns the value of CPSR (Current Program Status Register). */
  74. GEN_STATUS_READ(current, cpsr)
  75.  
  76.  
  77. /** Sets control bits of CPSR. */
  78. GEN_STATUS_WRITE(current, cpsr, control, c);
  79.  
  80.  
  81. /** Returns the value of SPSR (Saved Program Status Register). */
  82. GEN_STATUS_READ(saved, spsr)
  83.  
  84.  
  85. #endif
  86.  
  87. /** @}
  88.  */
  89.