/*
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32boot
* @{
*/
/** @file
*/
#include "mm.h"
/** Initializes section page table entry.
*
* Will be readable/writable by kernel with no access from user mode.
* Will belong to domain 0. No cache or buffering is enabled.
*
* \param pte page table entry to set
* \param frame first frame in the section (frame number)
* \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
*/
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){
pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
pte->bufferable = 0; // disable
pte->cacheable = 0;
pte->machine_depend = 0;
pte->domain = 0;
pte->should_be_zero_1 = 0;
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
pte->should_be_zero_2 = 0;
pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
};
void mm_kernel_mapping(void) {
int i;
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
// create 1:1 mapping (in lower 2GB)
for(i = 0; i < first_kernel_section; i++) {
init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION);
}
// create kernel mapping (in upper 2GB), physical addresses starting from 0
for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) {
init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION);
}
set_ptl0_address(page_table);
// enable paging
asm volatile (
"ldr r0, =0x55555555 \n"
"mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables
"mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system
"ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled
"and r0, r0, r1 \n"
"ldr r1, =0x00000001 \n" // mask to enable paging
"orr r0, r0, r1 \n"
"mcr p15, 0, r0, c1, c0, 0 \n" // store settings
:
:
: "r0", "r1"
);
};
/** @}
*/