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  1. /*
  2.  * Copyright (c) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32mm
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34. #include "mm.h"
  35.  
  36. void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){
  37.     pte->descriptor_type   = pte_descriptor_section;
  38.     pte->bufferable        = 0; // disable
  39.     pte->cacheable         = 0;
  40.     pte->machine_depend    = 0;
  41.     pte->domain            = 0;
  42.     pte->should_be_zero_1  = 0;
  43.     pte->access_permission =  pte_ap_user_no_kernel_rw;
  44.     pte->should_be_zero_2  = 0;
  45.     pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
  46. };
  47.  
  48.  
  49. // set memory mapping for kernel
  50. void mm_kernel_mapping(void) {
  51.     int i;
  52.     // Create 1:1 mapping
  53.     for( i=0; i < 4096; i++)
  54.         init_pte_level0_section_entry(&page_table[i+0000], i * FRAMES_PER_SECTION);
  55.  
  56.     // Create Kernel mapping
  57.     const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
  58.     for( i = offset; i < 4096; i++)
  59.         init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION);
  60.    
  61.     SET_PTL0_ADDRESS_ARCH( page_table);
  62.    
  63.     // enable paging
  64.     asm volatile (
  65.         "ldr r0, =0x55555555       \n"
  66.         "mcr p15, 0, r0, c3, c0, 0 \n" //set domain acces rights to client <==> take rights from page tables
  67.         "mrc p15, 0, r0, c1, c0, 0 \n" // get current setting of system ... register 1 isn't only for memmory management
  68.         "ldr r1, =0xFFFFFE8D       \n" // mask to disable aligment checks, System, Rom bit disable
  69.         "and r0, r0, r1            \n"
  70.         "ldr r1, =0x00000001       \n" // mask to enable paging
  71.         "orr r0, r0, r1            \n"
  72.         "mcr p15, 0, r0, c1, c0, 0 \n" // store setting
  73.         :
  74.         :
  75.         : "r0", "r1"
  76.     );
  77. };
  78.  
  79. /** @}
  80.  */
  81.  
  82.