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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __mips32_CP0_H__
  30. #define __mips32_CP0_H__
  31.  
  32. #include <arch/types.h>
  33.  
  34. #define cp0_status_ie_enabled_bit   (1<<0)
  35. #define cp0_status_exl_exception_bit    (1<<1)
  36. #define cp0_status_erl_error_bit    (1<<2)
  37. #define cp0_status_um_bit           (1<<4)
  38. #define cp0_status_bev_bootstrap_bit    (1<<22)
  39. #define cp0_status_fpu_bit              (1<<29)
  40.  
  41. #define cp0_status_im_shift     8
  42. #define cp0_status_im_mask              0xff00
  43.  
  44. #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
  45. #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
  46.  
  47. #define fpu_cop_id 1
  48.  
  49. /*
  50.  * Magic value for use in msim.
  51.  * On AMD Duron 800Mhz, this roughly seems like one us.
  52.  */
  53. #define cp0_compare_value       10000
  54.  
  55. #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
  56. #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
  57. #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
  58. #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
  59.  
  60. extern  __u32 cp0_index_read(void);
  61. extern void cp0_index_write(__u32 val);
  62.  
  63. extern __u32 cp0_random_read(void);
  64.  
  65. extern __u32 cp0_entry_lo0_read(void);
  66. extern void cp0_entry_lo0_write(__u32 val);
  67.  
  68. extern __u32 cp0_entry_lo1_read(void);
  69. extern void cp0_entry_lo1_write(__u32 val);
  70.  
  71. extern __u32 cp0_context_read(void);
  72. extern void cp0_context_write(__u32 val);
  73.  
  74. extern __u32 cp0_pagemask_read(void);
  75. extern void cp0_pagemask_write(__u32 val);
  76.  
  77. extern __u32 cp0_wired_read(void);
  78. extern void cp0_wired_write(__u32 val);
  79.  
  80. extern __u32 cp0_badvaddr_read(void);
  81.  
  82. extern volatile __u32 cp0_count_read(void);
  83. extern void cp0_count_write(__u32 val);
  84.  
  85. extern volatile __u32 cp0_entry_hi_read(void);
  86. extern void cp0_entry_hi_write(__u32 val);
  87.  
  88. extern volatile __u32 cp0_compare_read(void);
  89. extern void cp0_compare_write(__u32 val);
  90.  
  91. extern __u32 cp0_status_read(void);
  92. extern void cp0_status_write(__u32 val);
  93.  
  94. extern __u32 cp0_cause_read(void);
  95. extern void cp0_cause_write(__u32 val);
  96.  
  97. extern __u32 cp0_epc_read(void);
  98. extern void cp0_epc_write(__u32 val);
  99.  
  100. extern __u32 cp0_prid_read(void);
  101.  
  102. #endif
  103.