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| Rev 1123 | Rev 1660 | ||
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| Line 35... | Line 35... | ||
| 35 | #include <arch/asm/regname.h> |
35 | #include <arch/asm/regname.h> |
| 36 | #include <libarch/context_offset.h> |
36 | #include <libarch/context_offset.h> |
| 37 | 37 | ||
| 38 | .global context_save |
38 | .global context_save |
| 39 | .global context_restore |
39 | .global context_restore |
| 40 | 40 | ||
| 41 | .macro CONTEXT_STORE r |
41 | .macro CONTEXT_STORE r |
| 42 | sw $s0,OFFSET_S0(\r) |
42 | sw $s0,OFFSET_S0(\r) |
| 43 | sw $s1,OFFSET_S1(\r) |
43 | sw $s1,OFFSET_S1(\r) |
| 44 | sw $s2,OFFSET_S2(\r) |
44 | sw $s2,OFFSET_S2(\r) |
| 45 | sw $s3,OFFSET_S3(\r) |
45 | sw $s3,OFFSET_S3(\r) |
| Line 48... | Line 48... | ||
| 48 | sw $s6,OFFSET_S6(\r) |
48 | sw $s6,OFFSET_S6(\r) |
| 49 | sw $s7,OFFSET_S7(\r) |
49 | sw $s7,OFFSET_S7(\r) |
| 50 | sw $s8,OFFSET_S8(\r) |
50 | sw $s8,OFFSET_S8(\r) |
| 51 | sw $gp,OFFSET_GP(\r) |
51 | sw $gp,OFFSET_GP(\r) |
| 52 | sw $k1,OFFSET_TLS(\r) |
52 | sw $k1,OFFSET_TLS(\r) |
| - | 53 | ||
| - | 54 | #ifdef CONFIG_MIPS_FPU |
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| - | 55 | mfc1 $t0,$20 |
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| - | 56 | sw $t0, OFFSET_F20(\r) |
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| - | 57 | ||
| - | 58 | mfc1 $t0,$21 |
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| - | 59 | sw $t0, OFFSET_F21(\r) |
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| - | 60 | ||
| - | 61 | mfc1 $t0,$22 |
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| - | 62 | sw $t0, OFFSET_F22(\r) |
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| - | 63 | ||
| - | 64 | mfc1 $t0,$23 |
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| - | 65 | sw $t0, OFFSET_F23(\r) |
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| - | 66 | ||
| - | 67 | mfc1 $t0,$24 |
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| - | 68 | sw $t0, OFFSET_F24(\r) |
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| - | 69 | ||
| - | 70 | mfc1 $t0,$25 |
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| - | 71 | sw $t0, OFFSET_F25(\r) |
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| - | 72 | ||
| - | 73 | mfc1 $t0,$26 |
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| - | 74 | sw $t0, OFFSET_F26(\r) |
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| - | 75 | ||
| - | 76 | mfc1 $t0,$27 |
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| - | 77 | sw $t0, OFFSET_F27(\r) |
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| - | 78 | ||
| - | 79 | mfc1 $t0,$28 |
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| - | 80 | sw $t0, OFFSET_F28(\r) |
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| - | 81 | ||
| - | 82 | mfc1 $t0,$29 |
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| - | 83 | sw $t0, OFFSET_F29(\r) |
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| 53 | 84 | ||
| - | 85 | mfc1 $t0,$30 |
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| - | 86 | sw $t0, OFFSET_F30(\r) |
|
| - | 87 | #endif |
|
| - | 88 | ||
| 54 | sw $ra,OFFSET_PC(\r) |
89 | sw $ra,OFFSET_PC(\r) |
| 55 | sw $sp,OFFSET_SP(\r) |
90 | sw $sp,OFFSET_SP(\r) |
| 56 | .endm |
91 | .endm |
| 57 | 92 | ||
| 58 | .macro CONTEXT_LOAD r |
93 | .macro CONTEXT_LOAD r |
| Line 65... | Line 100... | ||
| 65 | lw $s6,OFFSET_S6(\r) |
100 | lw $s6,OFFSET_S6(\r) |
| 66 | lw $s7,OFFSET_S7(\r) |
101 | lw $s7,OFFSET_S7(\r) |
| 67 | lw $s8,OFFSET_S8(\r) |
102 | lw $s8,OFFSET_S8(\r) |
| 68 | lw $gp,OFFSET_GP(\r) |
103 | lw $gp,OFFSET_GP(\r) |
| 69 | lw $k1,OFFSET_TLS(\r) |
104 | lw $k1,OFFSET_TLS(\r) |
| - | 105 | ||
| - | 106 | #ifdef CONFIG_MIPS_FPU |
|
| - | 107 | lw $t0, OFFSET_F20(\r) |
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| - | 108 | mtc1 $t0,$20 |
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| - | 109 | ||
| - | 110 | lw $t0, OFFSET_F21(\r) |
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| - | 111 | mtc1 $t0,$21 |
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| - | 112 | ||
| - | 113 | lw $t0, OFFSET_F22(\r) |
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| - | 114 | mtc1 $t0,$22 |
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| - | 115 | ||
| - | 116 | lw $t0, OFFSET_F23(\r) |
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| - | 117 | mtc1 $t0,$23 |
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| - | 118 | ||
| - | 119 | lw $t0, OFFSET_F24(\r) |
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| - | 120 | mtc1 $t0,$24 |
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| - | 121 | ||
| - | 122 | lw $t0, OFFSET_F25(\r) |
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| - | 123 | mtc1 $t0,$25 |
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| - | 124 | ||
| - | 125 | lw $t0, OFFSET_F26(\r) |
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| - | 126 | mtc1 $t0,$26 |
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| - | 127 | ||
| - | 128 | lw $t0, OFFSET_F27(\r) |
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| - | 129 | mtc1 $t0,$27 |
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| - | 130 | ||
| - | 131 | lw $t0, OFFSET_F28(\r) |
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| - | 132 | mtc1 $t0,$28 |
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| - | 133 | ||
| - | 134 | lw $t0, OFFSET_F29(\r) |
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| - | 135 | mtc1 $t0,$29 |
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| - | 136 | ||
| - | 137 | lw $t0, OFFSET_F30(\r) |
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| - | 138 | mtc1 $t0,$30 |
|
| - | 139 | #endif |
|
| 70 | 140 | ||
| 71 | lw $ra,OFFSET_PC(\r) |
141 | lw $ra,OFFSET_PC(\r) |
| 72 | lw $sp,OFFSET_SP(\r) |
142 | lw $sp,OFFSET_SP(\r) |
| 73 | .endm |
143 | .endm |
| 74 | 144 | ||
| 75 | context_save: |
145 | context_save: |