Rev 550 | Rev 554 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 550 | Rev 551 | ||
|---|---|---|---|
| 1 | ## General configuration directives |
1 | ## General configuration directives |
| 2 | 2 | ||
| 3 | # Architecture |
3 | # Architecture |
| 4 | @ "ia32" Intel IA32 |
4 | @ "ia32" Intel IA-32 |
| 5 | @ "amd64" Intel ET64/AMD64 |
5 | @ "amd64" AMD64/Intel EM64T |
| 6 | @ "ia64" Intel IA64 |
6 | @ "ia64" Intel IA-64 |
| 7 | @ "mips32" MIPS 32-bit |
7 | @ "mips32" MIPS 32-bit |
| 8 | @ "ppc32" PowerPC 32-bit |
8 | @ "ppc32" PowerPC 32-bit |
| 9 | @ "sparc64" Sun UltraSparc 64-bit |
9 | @ "sparc64" Sun UltraSPARC |
| 10 | ! ARCH (choice) |
10 | ! ARCH (choice) |
| 11 | 11 | ||
| 12 | %ASKDEFAULT |
12 | %ASKDEFAULT |
| 13 | 13 | ||
| 14 | # IA32 Compiler |
14 | # IA32 Compiler |
| 15 | @ "cross" Cross-compiler |
15 | @ "cross" Cross-compiler |
| 16 | @ "native" Native |
16 | @ "native" Native |
| 17 | ! [ARCH=ia32] IA32_COMPILER (choice) |
17 | ! [ARCH=ia32] IA32_COMPILER (choice) |
| 18 | % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER |
18 | % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER |
| 19 | 19 | ||
| 20 | # AMD64 Compiler |
20 | # AMD64 Compiler |
| 21 | @ "cross" Cross-compiler |
21 | @ "cross" Cross-compiler |
| 22 | @ "native" Native |
22 | @ "native" Native |
| 23 | ! [ARCH=amd64] AMD64_COMPILER (choice) |
23 | ! [ARCH=amd64] AMD64_COMPILER (choice) |
| 24 | % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER |
24 | % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER |
| 25 | 25 | ||
| 26 | # Compiler |
26 | # Compiler |
| 27 | @ "cross" Cross-compiler |
27 | @ "cross" Cross-compiler |
| 28 | @ "native" Native |
28 | @ "native" Native |
| 29 | ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice) |
29 | ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice) |
| 30 | % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER |
30 | % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER |
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | # CPU type |
33 | # CPU type |
| 34 | @ "pentium4" Pentium 4 |
34 | @ "pentium4" Pentium 4 |
| 35 | @ "pentium3" Pentium 3 |
35 | @ "pentium3" Pentium 3 |
| 36 | @ "athlon-xp" Athlon XP |
36 | @ "athlon-xp" Athlon XP |
| 37 | @ "athlon-mp" Athlon MP |
37 | @ "athlon-mp" Athlon MP |
| 38 | @ "prescott" Prescott |
38 | @ "prescott" Prescott |
| 39 | ! [ARCH=ia32] IA32_CPU (choice) |
39 | ! [ARCH=ia32] IA32_CPU (choice) |
| 40 | 40 | ||
| 41 | # Support for SMP |
41 | # Support for SMP |
| 42 | ! CONFIG_SMP (y/n) |
42 | ! CONFIG_SMP (y/n) |
| 43 | 43 | ||
| 44 | # Improved support for hyperthreading |
44 | # Improved support for hyperthreading |
| 45 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
45 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
| 46 | 46 | ||
| 47 | # Lazy FPU context switching |
47 | # Lazy FPU context switching |
| 48 | ! CONFIG_FPU_LAZY (y/n) |
48 | ! CONFIG_FPU_LAZY (y/n) |
| 49 | 49 | ||
| 50 | # MIPS Machine Type |
50 | # MIPS Machine Type |
| 51 | @ "msim" MSIM Simulator |
51 | @ "msim" MSIM Simulator |
| 52 | @ "msim4kc" MSIM Simulator with 4kc instruction set |
52 | @ "msim4kc" MSIM Simulator with 4kc instruction set |
| 53 | @ "simics" Virtutech Simics simulator |
53 | @ "simics" Virtutech Simics simulator |
| 54 | @ "lgxemul" GXEmul Little Endian |
54 | @ "lgxemul" GXEmul Little Endian |
| 55 | @ "bgxemul" GXEmul Big Endian |
55 | @ "bgxemul" GXEmul Big Endian |
| 56 | @ "indy" SGI Indy |
56 | @ "indy" SGI Indy |
| 57 | ! [ARCH=mips32] MIPS_MACHINE (choice) |
57 | ! [ARCH=mips32] MIPS_MACHINE (choice) |
| 58 | 58 | ||
| 59 | ## Debugging configuration directives |
59 | ## Debugging configuration directives |
| 60 | 60 | ||
| 61 | # General debuging and assert checking |
61 | # General debuging and assert checking |
| 62 | ! CONFIG_DEBUG (y/n) |
62 | ! CONFIG_DEBUG (y/n) |
| 63 | 63 | ||
| 64 | # Deadlock detection support for spinlocks |
64 | # Deadlock detection support for spinlocks |
| 65 | ! [CONFIG_DEBUG=y] CONFIG_DEBUG_SPINLOCK (y/n) |
65 | ! [CONFIG_DEBUG=y] CONFIG_DEBUG_SPINLOCK (y/n) |
| 66 | 66 | ||
| 67 | ## Run-time configuration directives |
67 | ## Run-time configuration directives |
| 68 | 68 | ||
| 69 | # Enable user space support |
69 | # Enable user space support |
| 70 | ! CONFIG_USERSPACE (n/y) |
70 | ! CONFIG_USERSPACE (n/y) |
| 71 | 71 | ||
| 72 | # Kernel test type |
72 | # Kernel test type |
| 73 | @ "" No test |
73 | @ "" No test |
| 74 | @ "synch/rwlock1" Read write test 1 |
74 | @ "synch/rwlock1" Read write test 1 |
| 75 | @ "synch/rwlock2" Read write test 2 |
75 | @ "synch/rwlock2" Read write test 2 |
| 76 | @ "synch/rwlock3" Read write test 3 |
76 | @ "synch/rwlock3" Read write test 3 |
| 77 | @ "synch/rwlock4" Read write test 4 |
77 | @ "synch/rwlock4" Read write test 4 |
| 78 | @ "synch/rwlock5" Read write test 5 |
78 | @ "synch/rwlock5" Read write test 5 |
| 79 | @ "synch/semaphore1" Semaphore test 1 |
79 | @ "synch/semaphore1" Semaphore test 1 |
| 80 | @ "synch/semaphore2" Sempahore test 2 |
80 | @ "synch/semaphore2" Sempahore test 2 |
| 81 | @ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1 |
81 | @ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1 |
| 82 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
82 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
| 83 | @ [ARCH=mips] "fpu/mips1" Mips FPU test 1 |
83 | @ [ARCH=mips] "fpu/mips1" Mips FPU test 1 |
| 84 | @ "print/print1" Printf test 1 |
84 | @ "print/print1" Printf test 1 |
| 85 | @ "thread/trhead1" Thread test 1 |
85 | @ "thread/trhead1" Thread test 1 |
| 86 | @ "mm/mapping1" Mapping test 1 |
86 | @ "mm/mapping1" Mapping test 1 |
| 87 | ! CONFIG_TEST (choice) |
87 | ! CONFIG_TEST (choice) |
| 88 | 88 | ||