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| 1 | ## General configuration directives |
1 | ## General configuration directives |
| 2 | 2 | ||
| 3 | # Architecture |
3 | # Architecture |
| 4 | @ "ia32" Intel IA-32 |
4 | @ "ia32" Intel IA-32 |
| 5 | @ "amd64" AMD64/Intel EM64T |
5 | @ "amd64" AMD64/Intel EM64T |
| 6 | @ "ia64" Intel IA-64 |
6 | @ "ia64" Intel IA-64 |
| 7 | @ "mips32" MIPS 32-bit |
7 | @ "mips32" MIPS 32-bit |
| 8 | @ "ppc32" PowerPC 32-bit |
8 | @ "ppc32" PowerPC 32-bit |
| 9 | @ "sparc64" Sun UltraSPARC |
9 | @ "sparc64" Sun UltraSPARC |
| 10 | ! ARCH (choice) |
10 | ! ARCH (choice) |
| 11 | 11 | ||
| 12 | # IA32 Compiler |
12 | # IA32 Compiler |
| 13 | @ "cross" Cross-compiler |
13 | @ "cross" Cross-compiler |
| 14 | @ "native" Native |
14 | @ "native" Native |
| 15 | ! [ARCH=ia32] IA32_COMPILER (choice) |
15 | ! [ARCH=ia32] IA32_COMPILER (choice) |
| 16 | % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER |
16 | % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER |
| 17 | 17 | ||
| 18 | # AMD64 Compiler |
18 | # AMD64 Compiler |
| 19 | @ "cross" Cross-compiler |
19 | @ "cross" Cross-compiler |
| 20 | @ "native" Native |
20 | @ "native" Native |
| 21 | ! [ARCH=amd64] AMD64_COMPILER (choice) |
21 | ! [ARCH=amd64] AMD64_COMPILER (choice) |
| 22 | % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER |
22 | % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER |
| 23 | 23 | ||
| 24 | # Compiler |
24 | # Compiler |
| 25 | @ "cross" Cross-compiler |
25 | @ "cross" Cross-compiler |
| 26 | @ "native" Native |
26 | @ "native" Native |
| 27 | ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice) |
27 | ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice) |
| 28 | % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER |
28 | % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER |
| 29 | 29 | ||
| 30 | 30 | ||
| 31 | # CPU type |
31 | # CPU type |
| 32 | @ "pentium4" Pentium 4 |
32 | @ "pentium4" Pentium 4 |
| 33 | @ "pentium3" Pentium 3 |
33 | @ "pentium3" Pentium 3 |
| 34 | @ "athlon-xp" Athlon XP |
34 | @ "athlon-xp" Athlon XP |
| 35 | @ "athlon-mp" Athlon MP |
35 | @ "athlon-mp" Athlon MP |
| 36 | @ "prescott" Prescott |
36 | @ "prescott" Prescott |
| 37 | ! [ARCH=ia32] IA32_CPU (choice) |
37 | ! [ARCH=ia32] IA32_CPU (choice) |
| 38 | 38 | ||
| 39 | # MIPS Machine Type |
39 | # MIPS Machine Type |
| 40 | @ "msim" MSIM Simulator |
40 | @ "msim" MSIM Simulator |
| 41 | @ "simics" Virtutech Simics simulator |
41 | @ "simics" Virtutech Simics simulator |
| 42 | @ "lgxemul" GXEmul Little Endian |
42 | @ "lgxemul" GXEmul Little Endian |
| 43 | @ "bgxemul" GXEmul Big Endian |
43 | @ "bgxemul" GXEmul Big Endian |
| 44 | @ "indy" SGI Indy |
44 | @ "indy" SGI Indy |
| 45 | ! [ARCH=mips32] MIPS_MACHINE (choice) |
45 | ! [ARCH=mips32] MIPS_MACHINE (choice) |
| 46 | 46 | ||
| 47 | # Framebuffer support |
47 | # Framebuffer support |
| 48 | ! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n) |
48 | ! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n) |
| 49 | 49 | ||
| 50 | # Support for SMP |
50 | # Support for SMP |
| 51 | ! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n) |
51 | ! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n) |
| 52 | 52 | ||
| 53 | # Improved support for hyperthreading |
53 | # Improved support for hyperthreading |
| 54 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
54 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
| 55 | 55 | ||
| 56 | # Simics BIOS AP boot fix |
56 | # Simics BIOS AP boot fix |
| 57 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n) |
57 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n) |
| 58 | 58 | ||
| 59 | # Lazy FPU context switching |
59 | # Lazy FPU context switching |
| 60 | ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64] CONFIG_FPU_LAZY (y/n) |
60 | ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64] CONFIG_FPU_LAZY (y/n) |
| 61 | 61 | ||
| 62 | # Power off on halt |
62 | # Power off on halt |
| 63 | ! [ARCH=ppc32] CONFIG_POWEROFF (y/n) |
63 | ! [ARCH=ppc32] CONFIG_POWEROFF (y/n) |
| 64 | 64 | ||
| 65 | ## Debugging configuration directives |
65 | ## Debugging configuration directives |
| 66 | 66 | ||
| 67 | # General debuging and assert checking |
67 | # General debuging and assert checking |
| 68 | ! CONFIG_DEBUG (y/n) |
68 | ! CONFIG_DEBUG (y/n) |
| 69 | 69 | ||
| 70 | # Deadlock detection support for spinlocks |
70 | # Deadlock detection support for spinlocks |
| 71 | ! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n) |
71 | ! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n) |
| 72 | 72 | ||
| 73 | # Watchpoint on rewriting AS with zero |
73 | # Watchpoint on rewriting AS with zero |
| 74 | ! [CONFIG_DEBUG=y&ARCH=amd64] CONFIG_DEBUG_AS_WATCHPOINT (y/n) |
74 | ! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n) |
| 75 | 75 | ||
| 76 | ## Run-time configuration directives |
76 | ## Run-time configuration directives |
| 77 | 77 | ||
| 78 | # Kernel test type |
78 | # Kernel test type |
| 79 | @ "" No test |
79 | @ "" No test |
| 80 | @ "atomic/atomic1" Test of atomic operations. |
80 | @ "atomic/atomic1" Test of atomic operations. |
| 81 | @ "synch/rwlock1" Read write test 1 |
81 | @ "synch/rwlock1" Read write test 1 |
| 82 | @ "synch/rwlock2" Read write test 2 |
82 | @ "synch/rwlock2" Read write test 2 |
| 83 | @ "synch/rwlock3" Read write test 3 |
83 | @ "synch/rwlock3" Read write test 3 |
| 84 | @ "synch/rwlock4" Read write test 4 |
84 | @ "synch/rwlock4" Read write test 4 |
| 85 | @ "synch/rwlock5" Read write test 5 |
85 | @ "synch/rwlock5" Read write test 5 |
| 86 | @ "synch/semaphore1" Semaphore test 1 |
86 | @ "synch/semaphore1" Semaphore test 1 |
| 87 | @ "synch/semaphore2" Sempahore test 2 |
87 | @ "synch/semaphore2" Sempahore test 2 |
| 88 | @ [ARCH=ia32|ARCH=amd64|ARCH=ia64] "fpu/fpu1" Intel fpu test 1 |
88 | @ [ARCH=ia32|ARCH=amd64|ARCH=ia64] "fpu/fpu1" Intel fpu test 1 |
| 89 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
89 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
| 90 | @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1 |
90 | @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1 |
| 91 | @ "print/print1" Printf test 1 |
91 | @ "print/print1" Printf test 1 |
| 92 | @ "thread/thread1" Thread test 1 |
92 | @ "thread/thread1" Thread test 1 |
| 93 | @ "mm/mapping1" Mapping test 1 |
93 | @ "mm/mapping1" Mapping test 1 |
| 94 | @ "mm/falloc1" Frame Allocation test 1 |
94 | @ "mm/falloc1" Frame Allocation test 1 |
| 95 | @ "mm/falloc2" Frame Allocation test 2 |
95 | @ "mm/falloc2" Frame Allocation test 2 |
| 96 | @ "mm/slab1" SLAB test1 - No CPU-cache |
96 | @ "mm/slab1" SLAB test1 - No CPU-cache |
| 97 | @ "mm/slab2" SLAB test2 - SMP CPU cache |
97 | @ "mm/slab2" SLAB test2 - SMP CPU cache |
| 98 | @ "fault/fault1" Write to NULL (maybe page fault) |
98 | @ "fault/fault1" Write to NULL (maybe page fault) |
| 99 | @ [ARCH=ia64] "mm/purge1" Itanium TLB purge test |
99 | @ [ARCH=ia64] "mm/purge1" Itanium TLB purge test |
| 100 | @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test |
100 | @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test |
| 101 | ! CONFIG_TEST (choice) |
101 | ! CONFIG_TEST (choice) |
| 102 | 102 | ||