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| Rev 703 | Rev 822 | ||
|---|---|---|---|
| 1 | Memory management |
1 | Memory management |
| 2 | ================= |
2 | ================= |
| 3 | 3 | ||
| 4 | 1. Virtual Address Translation |
4 | 1. Virtual Address Translation |
| 5 | 5 | ||
| 6 | 1.1 Hierarchical 4-level per address space page tables |
6 | 1.1 Hierarchical 4-level per address space page tables |
| 7 | 7 | ||
| 8 | SPARTAN kernel deploys generic interface for 4-level page tables |
8 | SPARTAN kernel deploys generic interface for 4-level page tables |
| 9 | for these architectures: amd64, ia32, mips32 and ppc32. In this |
9 | for these architectures: amd64, ia32, mips32 and ppc32. In this |
| 10 | setting, page tables are hierarchical and are not shared by |
10 | setting, page tables are hierarchical and are not shared by |
| 11 | address spaces (i.e. one set of page tables per address space). |
11 | address spaces (i.e. one set of page tables per address space). |
| 12 | 12 | ||
| 13 | 13 | ||
| 14 | VADDR |
14 | VADDR |
| 15 | +-----------------------------------------------------------------------------+ |
15 | +-----------------------------------------------------------------------------+ |
| 16 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
16 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
| 17 | +-----------------------------------------------------------------------------+ |
17 | +-----------------------------------------------------------------------------+ |
| 18 | 18 | ||
| 19 | 19 | ||
| 20 | PTL0 PTL1 PTL2 PTL3 |
20 | PTL0 PTL1 PTL2 PTL3 |
| 21 | +--------+ +--------+ +--------+ +--------+ |
21 | +--------+ +--------+ +--------+ +--------+ |
| 22 | | | | | | PTL3 | -----\ | | |
22 | | | | | | PTL3 | -----\ | | |
| 23 | | | | | +--------+ | | | |
23 | | | | | +--------+ | | | |
| 24 | | | +--------+ | | | | | |
24 | | | +--------+ | | | | | |
| 25 | | | | PTL2 | -----\ | | | | | |
25 | | | | PTL2 | -----\ | | | | | |
| 26 | | | +--------+ | | | | | | |
26 | | | +--------+ | | | | | | |
| 27 | | | | | | | | | +--------+ |
27 | | | | | | | | | +--------+ |
| 28 | +--------+ | | | | | | | FRAME | |
28 | +--------+ | | | | | | | FRAME | |
| 29 | | PTL1 | -----\ | | | | | | +--------+ |
29 | | PTL1 | -----\ | | | | | | +--------+ |
| 30 | +--------+ | | | | | | | | | |
30 | +--------+ | | | | | | | | | |
| 31 | | | | | | | | | | | | |
31 | | | | | | | | | | | | |
| 32 | | | | | | | | | | | | |
32 | | | | | | | | | | | | |
| 33 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+ |
33 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+ |
| 34 | ^ |
34 | ^ |
| 35 | | |
35 | | |
| 36 | | |
36 | | |
| 37 | +--------+ |
37 | +--------+ |
| 38 | | PTL0 | |
38 | | PTL0 | |
| 39 | +--------+ |
39 | +--------+ |
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | PTL0 Page Table Level 0 (Page Directory) |
42 | PTL0 Page Table Level 0 (Page Directory) |
| 43 | PTL1 Page Table Level 1 |
43 | PTL1 Page Table Level 1 |
| 44 | PTL2 Page Table Level 2 |
44 | PTL2 Page Table Level 2 |
| 45 | PTL3 Page Table Level 3 |
45 | PTL3 Page Table Level 3 |
| 46 | 46 | ||
| 47 | PTL0_INDEX Index into PTL0 |
47 | PTL0_INDEX Index into PTL0 |
| 48 | PTL1_INDEX Index into PTL1 |
48 | PTL1_INDEX Index into PTL1 |
| 49 | PTL2_INDEX Index into PTL2 |
49 | PTL2_INDEX Index into PTL2 |
| 50 | PTL3_INDEX Index into PTL3 |
50 | PTL3_INDEX Index into PTL3 |
| 51 | 51 | ||
| 52 | VADDR Virtual address for which mapping is looked up |
52 | VADDR Virtual address for which mapping is looked up |
| 53 | FRAME Physical address of memory frame to which VADDR is mapped |
53 | FRAME Physical address of memory frame to which VADDR is mapped |
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
56 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
| 57 | left out. TLB-only architectures are to define custom format for software page |
57 | left out. TLB-only architectures are to define custom format for software page |
| 58 | tables. |
58 | tables. |
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | 61 | ||
| 62 | 1.2 Single global page hash table |
62 | 1.2 Single global page hash table |
| 63 | 63 | ||
| 64 | Generic page hash table interface is deployed on 64-bit architectures without |
64 | Generic page hash table interface is deployed on 64-bit architectures without |
| 65 | implied hardware support for hierarchical page tables, i.e. ia64 and sparc64. |
65 | implied hardware support for hierarchical page tables, i.e. ia64 and sparc64. |
| 66 | There is only one global page hash table in the system shared by all address |
66 | There is only one global page hash table in the system shared by all address |
| 67 | spaces. |
67 | spaces. |
| - | 68 | ||
| - | 69 | 2.1 General allocator |
|
| - | 70 | ||
| - | 71 | 'malloc' function accepts flags as a second argument. The flags are directly |
|
| - | 72 | passed to the underlying frame_alloc function. |
|
| - | 73 | ||
| - | 74 | 1) If the flags parameter contains FRAME_ATOMIC, the allocator will not sleep. |
|
| - | 75 | The allocator CAN return NULL, when memory is not directly available. |
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| - | 76 | The caller MUST check if NULL was not returned |
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| - | 77 | ||
| - | 78 | 2) If the flags parameter does not contain FRAME_ATOMIC, the allocator |
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| - | 79 | will never return NULL, but it CAN sleep indefinitely. The caller |
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| - | 80 | does not have to check the return value. |
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| - | 81 | ||
| - | 82 | 3) The maximum size that can be allocated using malloc is 128K |
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| - | 83 | ||
| - | 84 | Rules 1) and 2) apply to slab_alloc as well. Using SLAB allocator |
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| - | 85 | to allocate too large values is not recommended. |
|
| - | 86 | ||
| 68 | 87 | ||