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Line 107... Line 107...
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    tlb_invalidate_all();
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    tlb_invalidate_all();
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    dmmu_enable();
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    dmmu_enable();
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    immu_enable();
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    immu_enable();
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}
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    /*
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     * Quick hack: map frame buffer
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     */
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    fr.address = FB_PHYS_ADDRESS;
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    pg.address = FB_VIRT_ADDRESS;
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    tag.value = ASID_KERNEL;
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    tag.vpn = pg.vpn;
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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/** Insert privileged mapping into DMMU TLB.
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    data.v = true;
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 *
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    data.size = PAGESIZE_4M;
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 * @param page Virtual page address.
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    data.pfn = fr.pfn;
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 * @param frame Physical frame address.
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    data.l = true;
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 * @param pagesize Page size.
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 * @param locked True for permanent mappings, false otherwise.
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 * @param cacheable True if the mapping is cacheable, false otherwise.
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    data.cp = 0;
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 */
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void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
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{
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    data.cv = 0;
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    tlb_tag_access_reg_t tag;
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    data.p = true;
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    tlb_data_t data;
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    data.w = true;
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    page_address_t pg;
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    data.g = true;
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    frame_address_t fr;
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    dtlb_data_in_write(data.value);
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    /*
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     * Quick hack: map keyboard
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     */
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    fr.address = KBD_PHYS_ADDRESS;
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    pg.address = page;
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    pg.address = KBD_VIRT_ADDRESS;
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    fr.address = frame;
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    tag.value = ASID_KERNEL;
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    tag.value = ASID_KERNEL;
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    tag.vpn = pg.vpn;
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    tag.vpn = pg.vpn;
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    dtlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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    data.value = 0;
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    data.v = true;
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    data.v = true;
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    data.size = PAGESIZE_8K;
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    data.size = pagesize;
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    data.pfn = fr.pfn;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.l = locked;
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    data.cp = 0;
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    data.cp = cacheable;
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    data.cv = 0;
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    data.cv = cacheable;
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    data.p = true;
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    data.p = true;
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    data.w = true;
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    data.w = true;
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    data.g = true;
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    data.g = true;
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    dtlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
Line 167... Line 156...
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/** DTLB miss handler. */
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/** DTLB miss handler. */
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void fast_data_access_mmu_miss(void)
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void fast_data_access_mmu_miss(void)
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{
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{
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    tlb_tag_access_reg_t tag;
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    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    __address tpc;
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    __address tpc;
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    char *tpc_str;
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    char *tpc_str;
175
 
163
 
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    tag.value = dtlb_tag_access_read();
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    tag.value = dtlb_tag_access_read();
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    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
165
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
Line 184... Line 172...
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    }
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    }
185
 
173
 
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    /*
174
    /*
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     * Identity map piece of faulting kernel address space.
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     * Identity map piece of faulting kernel address space.
188
     */
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     */
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    data.value = 0;
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    data.v = true;
-
 
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    data.size = PAGESIZE_8K;
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    data.pfn = tag.vpn;
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    data.l = false;
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    data.cp = 1;
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    data.cv = 1;
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    data.p = true;
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    data.w = true;
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    data.g = true;
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-
 
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    dtlb_data_in_write(data.value);
177
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
201
}
178
}
202
 
179
 
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/** DTLB protection fault handler. */
180
/** DTLB protection fault handler. */
204
void fast_data_access_protection(void)
181
void fast_data_access_protection(void)
205
{
182
{