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| Rev 646 | Rev 727 | ||
|---|---|---|---|
| Line 163... | Line 163... | ||
| 163 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
163 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
| 164 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
164 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
| 165 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
165 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
| 166 | } |
166 | } |
| 167 | 167 | ||
| 168 | /** Invalidate all ITLB and DLTB entries for specified page in specified address space. |
168 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
| 169 | * |
169 | * |
| 170 | * @param asid Address Space ID. |
170 | * @param asid Address Space ID. |
| 171 | * @param page Page which to sweep out from ITLB and DTLB. |
171 | * @param page First page which to sweep out from ITLB and DTLB. |
| - | 172 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
|
| 172 | */ |
173 | */ |
| 173 | void tlb_invalidate_page(asid_t asid, __address page) |
174 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
| 174 | { |
175 | { |
| - | 176 | int i; |
|
| - | 177 | ||
| - | 178 | for (i = 0; i < cnt; i++) { |
|
| 175 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
179 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
| 176 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
180 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
| 177 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
181 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
| - | 182 | } |
|
| 178 | } |
183 | } |