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| Rev 617 | Rev 619 | ||
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| Line 26... | Line 26... | ||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
| 30 | #include <mm/tlb.h> |
30 | #include <mm/tlb.h> |
| - | 31 | #include <arch/mm/frame.h> |
|
| - | 32 | #include <arch/mm/page.h> |
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| - | 33 | #include <arch/mm/mmu.h> |
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| 31 | #include <print.h> |
34 | #include <print.h> |
| 32 | #include <arch/types.h> |
35 | #include <arch/types.h> |
| 33 | #include <typedefs.h> |
36 | #include <typedefs.h> |
| - | 37 | #include <config.h> |
|
| 34 | 38 | ||
| - | 39 | /** Initialize ITLB and DTLB. |
|
| - | 40 | * |
|
| - | 41 | * The goal of this function is to disable MMU |
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| - | 42 | * so that both TLBs can be purged and new |
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| - | 43 | * kernel 4M locked entry can be installed. |
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| - | 44 | * After TLB is initialized, MMU is enabled |
|
| - | 45 | * again. |
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| - | 46 | */ |
|
| 35 | void tlb_arch_init(void) |
47 | void tlb_arch_init(void) |
| 36 | { |
48 | { |
| - | 49 | tlb_tag_access_reg_t tag; |
|
| - | 50 | tlb_data_t data; |
|
| - | 51 | frame_address_t fr; |
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| - | 52 | page_address_t pg; |
|
| - | 53 | ||
| - | 54 | fr.address = config.base; |
|
| - | 55 | pg.address = config.base; |
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| - | 56 | ||
| - | 57 | immu_disable(); |
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| - | 58 | dmmu_disable(); |
|
| - | 59 | ||
| - | 60 | /* |
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| - | 61 | * For simplicity, we do identity mapping of first 4M of memory. |
|
| - | 62 | * The very next change should be leaving the first 4M unmapped. |
|
| - | 63 | */ |
|
| - | 64 | tag.value = 0; |
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| - | 65 | tag.vpn = pg.vpn; |
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| - | 66 | ||
| - | 67 | itlb_tag_access_write(tag.value); |
|
| - | 68 | dtlb_tag_access_write(tag.value); |
|
| - | 69 | ||
| - | 70 | data.value = 0; |
|
| - | 71 | data.v = true; |
|
| - | 72 | data.size = PAGESIZE_4M; |
|
| - | 73 | data.pfn = fr.pfn; |
|
| - | 74 | data.l = true; |
|
| - | 75 | data.cp = 1; |
|
| - | 76 | data.cv = 1; |
|
| - | 77 | data.p = true; |
|
| - | 78 | data.w = true; |
|
| - | 79 | data.g = true; |
|
| - | 80 | ||
| - | 81 | itlb_data_in_write(data.value); |
|
| - | 82 | dtlb_data_in_write(data.value); |
|
| - | 83 | ||
| - | 84 | tlb_invalidate_all(); |
|
| - | 85 | ||
| - | 86 | dmmu_enable(); |
|
| - | 87 | immu_enable(); |
|
| 37 | } |
88 | } |
| 38 | 89 | ||
| 39 | /** Print contents of both TLBs. */ |
90 | /** Print contents of both TLBs. */ |
| 40 | void tlb_print(void) |
91 | void tlb_print(void) |
| 41 | { |
92 | { |
| Line 71... | Line 122... | ||
| 71 | tlb_tag_read_reg_t t; |
122 | tlb_tag_read_reg_t t; |
| 72 | 123 | ||
| 73 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
124 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
| 74 | d.value = itlb_data_access_read(i); |
125 | d.value = itlb_data_access_read(i); |
| 75 | if (!d.l) { |
126 | if (!d.l) { |
| 76 | printf("invalidating "); |
- | |
| 77 | t.value = itlb_tag_read_read(i); |
127 | t.value = itlb_tag_read_read(i); |
| 78 | d.v = false; |
128 | d.v = false; |
| 79 | itlb_tag_access_write(t.value); |
129 | itlb_tag_access_write(t.value); |
| 80 | itlb_data_access_write(i, d.value); |
130 | itlb_data_access_write(i, d.value); |
| 81 | } |
131 | } |