WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup sparc64mm 
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
#include <arch/drivers/fb.h>
#include <arch/drivers/i8042.h>
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
/** Initialize ITLB and DTLB.
 *
 * The goal of this function is to disable MMU
 * so that both TLBs can be purged and new
 * kernel 4M locked entry can be installed.
 * After TLB is initialized, MMU is enabled
 * again.
 *
 * Switching MMU off imposes the requirement for
 * the kernel to run in identity mapped environment.
 */
void tlb_arch_init(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    frame_address_t fr;
    page_address_t pg;
 
    fr.address = config.base;
    pg.address = config.base;
 
    immu_disable();
    dmmu_disable();
 
    /*
     * Demap everything, especially OpenFirmware.
     */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
   
    /*
     * We do identity mapping of 4M-page at 4M.
     */
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    itlb_tag_access_write(tag.value);
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    itlb_data_in_write(data.value);
    dtlb_data_in_write(data.value);
 
    /*
     * Register window traps can occur before MMU is enabled again.
     * This ensures that any such traps will be handled from
     * kernel identity mapped trap handler.
     */
    trap_switch_trap_table();
   
    tlb_invalidate_all();
 
    dmmu_enable();
    immu_enable();
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_tag_access_reg_t tag;
    uintptr_t tpc;
    char *tpc_str;
 
    tag.value = dtlb_tag_access_read();
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
        tpc = tpc_read();
        tpc_str = get_symtab_entry(tpc);
 
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
        panic("%s\n", __FUNCTION__);
    }
 
    /*
     * Identity map piece of faulting kernel address space.
     */
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 
 /** @}
 */
 
 

Rev 1735	Rev 1780
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <arch/mm/frame.h>	37	#include <arch/mm/frame.h>
38	#include <arch/mm/page.h>	38	#include <arch/mm/page.h>
39	#include <arch/mm/mmu.h>	39	#include <arch/mm/mmu.h>
40	#include <mm/asid.h>	40	#include <mm/asid.h>
41	#include <print.h>	41	#include <print.h>
42	#include <arch/types.h>	42	#include <arch/types.h>
43	#include <typedefs.h>	43	#include <typedefs.h>
44	#include <config.h>	44	#include <config.h>
45	#include <arch/trap/trap.h>	45	#include <arch/trap/trap.h>
46	#include <panic.h>	46	#include <panic.h>
47	#include <arch/asm.h>	47	#include <arch/asm.h>
48	#include <symtab.h>	48	#include <symtab.h>
49		49
50	#include <arch/drivers/fb.h>	50	#include <arch/drivers/fb.h>
51	#include <arch/drivers/i8042.h>	51	#include <arch/drivers/i8042.h>
52		52
53	char *context_encoding[] = {	53	char *context_encoding[] = {
54	"Primary",	54	"Primary",
55	"Secondary",	55	"Secondary",
56	"Nucleus",	56	"Nucleus",
57	"Reserved"	57	"Reserved"
58	};	58	};
59		59
60	/** Initialize ITLB and DTLB.	60	/** Initialize ITLB and DTLB.
61	*	61	*
62	* The goal of this function is to disable MMU	62	* The goal of this function is to disable MMU
63	* so that both TLBs can be purged and new	63	* so that both TLBs can be purged and new
64	* kernel 4M locked entry can be installed.	64	* kernel 4M locked entry can be installed.
65	* After TLB is initialized, MMU is enabled	65	* After TLB is initialized, MMU is enabled
66	* again.	66	* again.
67	*	67	*
68	* Switching MMU off imposes the requirement for	68	* Switching MMU off imposes the requirement for
69	* the kernel to run in identity mapped environment.	69	* the kernel to run in identity mapped environment.
70	*/	70	*/
71	void tlb_arch_init(void)	71	void tlb_arch_init(void)
72	{	72	{
73	tlb_tag_access_reg_t tag;	73	tlb_tag_access_reg_t tag;
74	tlb_data_t data;	74	tlb_data_t data;
75	frame_address_t fr;	75	frame_address_t fr;
76	page_address_t pg;	76	page_address_t pg;
77		77
78	fr.address = config.base;	78	fr.address = config.base;
79	pg.address = config.base;	79	pg.address = config.base;
80		80
81	immu_disable();	81	immu_disable();
82	dmmu_disable();	82	dmmu_disable();
83		83
84	/*	84	/*
85	* Demap everything, especially OpenFirmware.	85	* Demap everything, especially OpenFirmware.
86	*/	86	*/
87	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	87	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
88	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	88	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
89		89
90	/*	90	/*
91	* We do identity mapping of 4M-page at 4M.	91	* We do identity mapping of 4M-page at 4M.
92	*/	92	*/
93	tag.value = ASID_KERNEL;	93	tag.value = ASID_KERNEL;
94	tag.vpn = pg.vpn;	94	tag.vpn = pg.vpn;
95		95
96	itlb_tag_access_write(tag.value);	96	itlb_tag_access_write(tag.value);
97	dtlb_tag_access_write(tag.value);	97	dtlb_tag_access_write(tag.value);
98		98
99	data.value = 0;	99	data.value = 0;
100	data.v = true;	100	data.v = true;
101	data.size = PAGESIZE_4M;	101	data.size = PAGESIZE_4M;
102	data.pfn = fr.pfn;	102	data.pfn = fr.pfn;
103	data.l = true;	103	data.l = true;
104	data.cp = 1;	104	data.cp = 1;
105	data.cv = 1;	105	data.cv = 1;
106	data.p = true;	106	data.p = true;
107	data.w = true;	107	data.w = true;
108	data.g = true;	108	data.g = true;
109		109
110	itlb_data_in_write(data.value);	110	itlb_data_in_write(data.value);
111	dtlb_data_in_write(data.value);	111	dtlb_data_in_write(data.value);
112		112
113	/*	113	/*
114	* Register window traps can occur before MMU is enabled again.	114	* Register window traps can occur before MMU is enabled again.
115	* This ensures that any such traps will be handled from	115	* This ensures that any such traps will be handled from
116	* kernel identity mapped trap handler.	116	* kernel identity mapped trap handler.
117	*/	117	*/
118	trap_switch_trap_table();	118	trap_switch_trap_table();
119		119
120	tlb_invalidate_all();	120	tlb_invalidate_all();
121		121
122	dmmu_enable();	122	dmmu_enable();
123	immu_enable();	123	immu_enable();
124	}	124	}
125		125
126	/** Insert privileged mapping into DMMU TLB.	126	/** Insert privileged mapping into DMMU TLB.
127	*	127	*
128	* @param page Virtual page address.	128	* @param page Virtual page address.
129	* @param frame Physical frame address.	129	* @param frame Physical frame address.
130	* @param pagesize Page size.	130	* @param pagesize Page size.
131	* @param locked True for permanent mappings, false otherwise.	131	* @param locked True for permanent mappings, false otherwise.
132	* @param cacheable True if the mapping is cacheable, false otherwise.	132	* @param cacheable True if the mapping is cacheable, false otherwise.
133	*/	133	*/
134	void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)	134	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
135	{	135	{
136	tlb_tag_access_reg_t tag;	136	tlb_tag_access_reg_t tag;
137	tlb_data_t data;	137	tlb_data_t data;
138	page_address_t pg;	138	page_address_t pg;
139	frame_address_t fr;	139	frame_address_t fr;
140		140
141	pg.address = page;	141	pg.address = page;
142	fr.address = frame;	142	fr.address = frame;
143		143
144	tag.value = ASID_KERNEL;	144	tag.value = ASID_KERNEL;
145	tag.vpn = pg.vpn;	145	tag.vpn = pg.vpn;
146		146
147	dtlb_tag_access_write(tag.value);	147	dtlb_tag_access_write(tag.value);
148		148
149	data.value = 0;	149	data.value = 0;
150	data.v = true;	150	data.v = true;
151	data.size = pagesize;	151	data.size = pagesize;
152	data.pfn = fr.pfn;	152	data.pfn = fr.pfn;
153	data.l = locked;	153	data.l = locked;
154	data.cp = cacheable;	154	data.cp = cacheable;
155	data.cv = cacheable;	155	data.cv = cacheable;
156	data.p = true;	156	data.p = true;
157	data.w = true;	157	data.w = true;
158	data.g = true;	158	data.g = true;
159		159
160	dtlb_data_in_write(data.value);	160	dtlb_data_in_write(data.value);
161	}	161	}
162		162
163	/** ITLB miss handler. */	163	/** ITLB miss handler. */
164	void fast_instruction_access_mmu_miss(void)	164	void fast_instruction_access_mmu_miss(void)
165	{	165	{
166	panic("%s\n", __FUNCTION__);	166	panic("%s\n", __FUNCTION__);
167	}	167	}
168		168
169	/** DTLB miss handler. */	169	/** DTLB miss handler. */
170	void fast_data_access_mmu_miss(void)	170	void fast_data_access_mmu_miss(void)
171	{	171	{
172	tlb_tag_access_reg_t tag;	172	tlb_tag_access_reg_t tag;
173	__address tpc;	173	uintptr_t tpc;
174	char *tpc_str;	174	char *tpc_str;
175		175
176	tag.value = dtlb_tag_access_read();	176	tag.value = dtlb_tag_access_read();
177	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {	177	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {
178	tpc = tpc_read();	178	tpc = tpc_read();
179	tpc_str = get_symtab_entry(tpc);	179	tpc_str = get_symtab_entry(tpc);
180		180
181	printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);	181	printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
182	printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");	182	printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
183	panic("%s\n", __FUNCTION__);	183	panic("%s\n", __FUNCTION__);
184	}	184	}
185		185
186	/*	186	/*
187	* Identity map piece of faulting kernel address space.	187	* Identity map piece of faulting kernel address space.
188	*/	188	*/
189	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);	189	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
190	}	190	}
191		191
192	/** DTLB protection fault handler. */	192	/** DTLB protection fault handler. */
193	void fast_data_access_protection(void)	193	void fast_data_access_protection(void)
194	{	194	{
195	panic("%s\n", __FUNCTION__);	195	panic("%s\n", __FUNCTION__);
196	}	196	}
197		197
198	/** Print contents of both TLBs. */	198	/** Print contents of both TLBs. */
199	void tlb_print(void)	199	void tlb_print(void)
200	{	200	{
201	int i;	201	int i;
202	tlb_data_t d;	202	tlb_data_t d;
203	tlb_tag_read_reg_t t;	203	tlb_tag_read_reg_t t;
204		204
205	printf("I-TLB contents:\n");	205	printf("I-TLB contents:\n");
206	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	206	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
207	d.value = itlb_data_access_read(i);	207	d.value = itlb_data_access_read(i);
208	t.value = itlb_tag_read_read(i);	208	t.value = itlb_tag_read_read(i);
209		209
210	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	210	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
211	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	211	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
212	}	212	}
213		213
214	printf("D-TLB contents:\n");	214	printf("D-TLB contents:\n");
215	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	215	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
216	d.value = dtlb_data_access_read(i);	216	d.value = dtlb_data_access_read(i);
217	t.value = dtlb_tag_read_read(i);	217	t.value = dtlb_tag_read_read(i);
218		218
219	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	219	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
220	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	220	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
221	}	221	}
222		222
223	}	223	}
224		224
225	/** Invalidate all unlocked ITLB and DTLB entries. */	225	/** Invalidate all unlocked ITLB and DTLB entries. */
226	void tlb_invalidate_all(void)	226	void tlb_invalidate_all(void)
227	{	227	{
228	int i;	228	int i;
229	tlb_data_t d;	229	tlb_data_t d;
230	tlb_tag_read_reg_t t;	230	tlb_tag_read_reg_t t;
231		231
232	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	232	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
233	d.value = itlb_data_access_read(i);	233	d.value = itlb_data_access_read(i);
234	if (!d.l) {	234	if (!d.l) {
235	t.value = itlb_tag_read_read(i);	235	t.value = itlb_tag_read_read(i);
236	d.v = false;	236	d.v = false;
237	itlb_tag_access_write(t.value);	237	itlb_tag_access_write(t.value);
238	itlb_data_access_write(i, d.value);	238	itlb_data_access_write(i, d.value);
239	}	239	}
240	}	240	}
241		241
242	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	242	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
243	d.value = dtlb_data_access_read(i);	243	d.value = dtlb_data_access_read(i);
244	if (!d.l) {	244	if (!d.l) {
245	t.value = dtlb_tag_read_read(i);	245	t.value = dtlb_tag_read_read(i);
246	d.v = false;	246	d.v = false;
247	dtlb_tag_access_write(t.value);	247	dtlb_tag_access_write(t.value);
248	dtlb_data_access_write(i, d.value);	248	dtlb_data_access_write(i, d.value);
249	}	249	}
250	}	250	}
251		251
252	}	252	}
253		253
254	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	254	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
255	*	255	*
256	* @param asid Address Space ID.	256	* @param asid Address Space ID.
257	*/	257	*/
258	void tlb_invalidate_asid(asid_t asid)	258	void tlb_invalidate_asid(asid_t asid)
259	{	259	{
260	/* TODO: write asid to some Context register and encode the register in second parameter below. */	260	/* TODO: write asid to some Context register and encode the register in second parameter below. */
261	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	261	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
262	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	262	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
263	}	263	}
264		264
265	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	265	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
266	*	266	*
267	* @param asid Address Space ID.	267	* @param asid Address Space ID.
268	* @param page First page which to sweep out from ITLB and DTLB.	268	* @param page First page which to sweep out from ITLB and DTLB.
269	* @param cnt Number of ITLB and DTLB entries to invalidate.	269	* @param cnt Number of ITLB and DTLB entries to invalidate.
270	*/	270	*/
271	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	271	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
272	{	272	{
273	int i;	273	int i;
274		274
275	for (i = 0; i < cnt; i++) {	275	for (i = 0; i < cnt; i++) {
276	/* TODO: write asid to some Context register and encode the register in second parameter below. */	276	/* TODO: write asid to some Context register and encode the register in second parameter below. */
277	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	277	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
278	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	278	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
279	}	279	}
280	}	280	}
281		281
282	/** @}	282	/** @}
283	*/	283	*/
284		284
285		285

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(root)/kernel/trunk/arch/sparc64/src/mm/tlb.c – Rev 1735 → 1780