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/*
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/*
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 * Copyright (C) 2005 Jakub Jermar
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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-
 
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 /** @addtogroup sparc64cpu sparc64
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 * @ingroup cpu
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 * @{
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 */
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/** @file
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 */
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#include <cpu.h>
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#include <cpu.h>
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#include <arch.h>
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#include <arch.h>
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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <print.h>
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#include <print.h>
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void cpu_arch_init(void)
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void cpu_arch_init(void)
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{
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{
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}
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}
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void cpu_identify(void)
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void cpu_identify(void)
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{
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{
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    CPU->arch.ver.value = ver_read();
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    CPU->arch.ver.value = ver_read();
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}
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}
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void cpu_print_report(cpu_t *m)
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void cpu_print_report(cpu_t *m)
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{
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{
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    char *manuf, *impl;
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    char *manuf, *impl;
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    switch (CPU->arch.ver.manuf) {
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    switch (CPU->arch.ver.manuf) {
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        case MANUF_FUJITSU:
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        case MANUF_FUJITSU:
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        manuf = "Fujitsu";
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        manuf = "Fujitsu";
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        break;
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        break;
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        case MANUF_ULTRASPARC:
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        case MANUF_ULTRASPARC:
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        manuf = "UltraSPARC";
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        manuf = "UltraSPARC";
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        break;
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        break;
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        case MANUF_SUN:
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        case MANUF_SUN:
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            manuf = "Sun";
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            manuf = "Sun";
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        break;
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        break;
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        default:
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        default:
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        manuf = "Unknown";
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        manuf = "Unknown";
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        break;
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        break;
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    }
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    }
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    switch (CPU->arch.ver.impl) {
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    switch (CPU->arch.ver.impl) {
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        case IMPL_ULTRASPARCI:
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        case IMPL_ULTRASPARCI:
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        impl = "UltraSPARC I";
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        impl = "UltraSPARC I";
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        break;
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        break;
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        case IMPL_ULTRASPARCII:
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        case IMPL_ULTRASPARCII:
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        impl = "UltraSPARC II";
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        impl = "UltraSPARC II";
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        break;
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        break;
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        case IMPL_ULTRASPARCII_I:
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        case IMPL_ULTRASPARCII_I:
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        impl = "UltraSPARC IIi";
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        impl = "UltraSPARC IIi";
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        break;
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        break;
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        case IMPL_ULTRASPARCII_E:
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        case IMPL_ULTRASPARCII_E:
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        impl = "UltraSPARC IIe";
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        impl = "UltraSPARC IIe";
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        break;
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        break;
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        case IMPL_ULTRASPARCIII:
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        case IMPL_ULTRASPARCIII:
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        impl = "UltraSPARC III";
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        impl = "UltraSPARC III";
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        break;
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        break;
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        case IMPL_ULTRASPARCIV_PLUS:
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        case IMPL_ULTRASPARCIV_PLUS:
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        impl = "UltraSPARC IV+";
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        impl = "UltraSPARC IV+";
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        break;
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        break;
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        case IMPL_SPARC64V:
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        case IMPL_SPARC64V:
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        impl = "SPARC 64V";
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        impl = "SPARC 64V";
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        break;
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        break;
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        default:
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        default:
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        impl = "Unknown";
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        impl = "Unknown";
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        break;
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        break;
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    }
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    }
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    printf("cpu%d: manuf=%s, impl=%s, mask=%d\n", CPU->id, manuf, impl, CPU->arch.ver.mask);
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    printf("cpu%d: manuf=%s, impl=%s, mask=%d\n", CPU->id, manuf, impl, CPU->arch.ver.mask);
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}
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}
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 /** @}
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 */
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