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 */
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 */
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#ifndef __sparc64_ASM_H__
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#ifndef __sparc64_ASM_H__
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#define __sparc64_ASM_H__
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#define __sparc64_ASM_H__
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#include <typedefs.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/register.h>
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#include <config.h>
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#include <config.h>
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/** Read Processor State register.
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 *
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 * @return Value of PSTATE register.
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 */
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static inline __u64 pstate_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
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    return v;
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}
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/** Write Processor State register.
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 *
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 * @param New value of PSTATE register.
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 */
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static inline void pstate_write(__u64 v)
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{
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    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
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}
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/** Enable interrupts.
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/** Enable interrupts.
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 *
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 *
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 * Enable interrupts and return previous
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 * Enable interrupts and return previous
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 * value of IPL.
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 * value of IPL.
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 *
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 *
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 * @return Old interrupt priority level.
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 * @return Old interrupt priority level.
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 */
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 */
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static inline ipl_t interrupts_enable(void) {
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static inline ipl_t interrupts_enable(void) {
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    pstate_reg_t pstate;
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    __u64 value;
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    value = pstate_read();
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    pstate.value = value;
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    pstate.ie = true;
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    pstate_write(pstate.value);
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    return (ipl_t) value;
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}
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}
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/** Disable interrupts.
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/** Disable interrupts.
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 *
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 *
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 * Disable interrupts and return previous
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 * Disable interrupts and return previous
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 * value of IPL.
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 * value of IPL.
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 *
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 *
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 * @return Old interrupt priority level.
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 * @return Old interrupt priority level.
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 */
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 */
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static inline ipl_t interrupts_disable(void) {
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static inline ipl_t interrupts_disable(void) {
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    pstate_reg_t pstate;
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    __u64 value;
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    value = pstate_read();
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    pstate.value = value;
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    pstate.ie = false;
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    pstate_write(pstate.value);
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    return (ipl_t) value;
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}
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}
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/** Restore interrupt priority level.
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/** Restore interrupt priority level.
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 *
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 *
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 * Restore IPL.
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 * Restore IPL.
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 *
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 *
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 * @param ipl Saved interrupt priority level.
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 * @param ipl Saved interrupt priority level.
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 */
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 */
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static inline void interrupts_restore(ipl_t ipl) {
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static inline void interrupts_restore(ipl_t ipl) {
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    pstate_reg_t pstate;
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    pstate.value = pstate_read();
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    pstate.ie = ((pstate_reg_t) ipl).ie;
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    pstate_write(pstate.value);
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}
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}
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/** Return interrupt priority level.
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/** Return interrupt priority level.
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 *
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 *
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 * Return IPL.
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 * Return IPL.
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 *
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 *
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 * @return Current interrupt priority level.
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 * @return Current interrupt priority level.
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 */
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 */
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static inline ipl_t interrupts_read(void) {
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static inline ipl_t interrupts_read(void) {
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    return (ipl_t) pstate_read();
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}
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}
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/** Return base address of current stack.
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/** Return base address of current stack.
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 *
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 *
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 * Return the base address of the current stack.
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 * Return the base address of the current stack.
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 */
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 */
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static inline __address get_stack_base(void)
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static inline __address get_stack_base(void)
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{
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{
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    __address v;
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    __address v;
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    __asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
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    return v;
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}
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}
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/** Read Version Register.
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/** Read Version Register.