WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __sparc64_ASM_H__
#define __sparc64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
   
    return v;
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline __u64 ver_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline __u64 tba_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param New value of TBA.
 */
static inline void tba_write(__u64 v)
{
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load __u64 from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline __u64 asi_u64_read(asi_t asi, __address va)
{
    __u64 v;
   
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
   
    return v;
}
 
/** Store __u64 to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
{
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
}
 
void cpu_halt(void);
void cpu_sleep(void);
void asm_delay_loop(__u32 t);
 
#endif
 

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/sparc64/include/asm.h – Rev 613 → 640

Rev 613		Rev 640
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __sparc64_ASM_H__	29	#ifndef __sparc64_ASM_H__
30	#define __sparc64_ASM_H__	30	#define __sparc64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	/** Enable interrupts.	35	/** Enable interrupts.
36	*	36	*
37	* Enable interrupts and return previous	37	* Enable interrupts and return previous
38	* value of IPL.	38	* value of IPL.
39	*	39	*
40	* @return Old interrupt priority level.	40	* @return Old interrupt priority level.
41	*/	41	*/
42	static inline ipl_t interrupts_enable(void) {	42	static inline ipl_t interrupts_enable(void) {
43	}	43	}
44		44
45	/** Disable interrupts.	45	/** Disable interrupts.
46	*	46	*
47	* Disable interrupts and return previous	47	* Disable interrupts and return previous
48	* value of IPL.	48	* value of IPL.
49	*	49	*
50	* @return Old interrupt priority level.	50	* @return Old interrupt priority level.
51	*/	51	*/
52	static inline ipl_t interrupts_disable(void) {	52	static inline ipl_t interrupts_disable(void) {
53	}	53	}
54		54
55	/** Restore interrupt priority level.	55	/** Restore interrupt priority level.
56	*	56	*
57	* Restore IPL.	57	* Restore IPL.
58	*	58	*
59	* @param ipl Saved interrupt priority level.	59	* @param ipl Saved interrupt priority level.
60	*/	60	*/
61	static inline void interrupts_restore(ipl_t ipl) {	61	static inline void interrupts_restore(ipl_t ipl) {
62	}	62	}
63		63
64	/** Return interrupt priority level.	64	/** Return interrupt priority level.
65	*	65	*
66	* Return IPL.	66	* Return IPL.
67	*	67	*
68	* @return Current interrupt priority level.	68	* @return Current interrupt priority level.
69	*/	69	*/
70	static inline ipl_t interrupts_read(void) {	70	static inline ipl_t interrupts_read(void) {
71	}	71	}
72		72
73	/** Return base address of current stack.	73	/** Return base address of current stack.
74	*	74	*
75	* Return the base address of the current stack.	75	* Return the base address of the current stack.
76	* The stack is assumed to be STACK_SIZE bytes long.	76	* The stack is assumed to be STACK_SIZE bytes long.
77	* The stack must start on page boundary.	77	* The stack must start on page boundary.
78	*/	78	*/
79	static inline __address get_stack_base(void)	79	static inline __address get_stack_base(void)
80	{	80	{
81	__address v;	81	__address v;
82		82
83	__asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));	83	__asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
84		84
85	return v;	85	return v;
86	}	86	}
87		87
-		88	/** Read Version Register.
-		89	*
-		90	* @return Value of VER register.
-		91	*/
-		92	static inline __u64 ver_read(void)
-		93	{
-		94	__u64 v;
-		95
-		96	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
-		97
-		98	return v;
-		99	}
-		100
88	/** Read Trap Base Address register.	101	/** Read Trap Base Address register.
89	*	102	*
90	* @return Current value in TBA.	103	* @return Current value in TBA.
91	*/	104	*/
92	static inline __u64 tba_read(void)	105	static inline __u64 tba_read(void)
93	{	106	{
94	__u64 v;	107	__u64 v;
95		108
96	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));	109	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
97		110
98	return v;	111	return v;
99	}	112	}
100		113
101	/** Write Trap Base Address register.	114	/** Write Trap Base Address register.
102	*	115	*
103	* @param New value of TBA.	116	* @param New value of TBA.
104	*/	117	*/
105	static inline void tba_write(__u64 v)	118	static inline void tba_write(__u64 v)
106	{	119	{
107	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	120	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
108	}	121	}
109		122
110	/** Load __u64 from alternate space.	123	/** Load __u64 from alternate space.
111	*	124	*
112	* @param asi ASI determining the alternate space.	125	* @param asi ASI determining the alternate space.
113	* @param va Virtual address within the ASI.	126	* @param va Virtual address within the ASI.
114	*	127	*
115	* @return Value read from the virtual address in the specified address space.	128	* @return Value read from the virtual address in the specified address space.
116	*/	129	*/
117	static inline __u64 asi_u64_read(asi_t asi, __address va)	130	static inline __u64 asi_u64_read(asi_t asi, __address va)
118	{	131	{
119	__u64 v;	132	__u64 v;
120		133
121	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));	134	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
122		135
123	return v;	136	return v;
124	}	137	}
125		138
126	/** Store __u64 to alternate space.	139	/** Store __u64 to alternate space.
127	*	140	*
128	* @param asi ASI determining the alternate space.	141	* @param asi ASI determining the alternate space.
129	* @param va Virtual address within the ASI.	142	* @param va Virtual address within the ASI.
130	* @param v Value to be written.	143	* @param v Value to be written.
131	*/	144	*/
132	static inline void asi_u64_write(asi_t asi, __address va, __u64 v)	145	static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
133	{	146	{
134	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");	147	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
135	}	148	}
136		149
137	void cpu_halt(void);	150	void cpu_halt(void);
138	void cpu_sleep(void);	151	void cpu_sleep(void);
139	void asm_delay_loop(__u32 t);	152	void asm_delay_loop(__u32 t);
140		153
141	#endif	154	#endif
142		155