WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (C) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as       Address space.
 * @param lock     Lock/unlock the address space.
 * @param badvaddr Faulting virtual address.
 * @param access   Access mode that caused the fault.
 * @param istate   Pointer to interrupted state.
 * @param pfrc     Pointer to variable where as_page_fault() return code will be stored.
 * @return         PTE on success, NULL otherwise.
 *
 */
static pte_t *find_mapping_and_check(as_t *as, bool lock, __address badvaddr, int access, istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->p)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
            case AS_PF_OK:
                /*
                 * The higher-level page fault handler succeeded,
                 * The mapping ought to be in place.
                 */
                page_table_lock(as, lock);
                pte = page_mapping_find(as, badvaddr);
                ASSERT((pte) && (pte->p));
                *pfrc = 0;
                return pte;
            case AS_PF_DEFER:
                page_table_lock(as, lock);
                *pfrc = rc;
                return NULL;
            case AS_PF_FAULT:
                page_table_lock(as, lock);
                printf("Page fault.\n");
                *pfrc = rc;
                return NULL;
            default:
                panic("unexpected rc (%d)\n", rc);
        }  
    }
}
 
 
static void pht_refill_fail(__address badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->pc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->lr);
    if (s)
        sym2 = s;
    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const __address vaddr, const pfn_t pfn)
{
    __u32 page = (vaddr >> 12) & 0xffff;
    __u32 api = (vaddr >> 22) & 0x3f;
   
    __u32 vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    __u32 sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    __u32 h = 0;
    __u32 hash = vsid ^ page;
    __u32 base = (hash & 0x3ff) << 3;
    __u32 i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        __u32 base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const __address vaddr, const pfn_t pfn)
{
    __u32 page = (vaddr >> 12) & 0xffff;
    __u32 api = (vaddr >> 22) & 0x3f;
   
    __u32 vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    __u32 sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    __u32 h = 0;
    __u32 hash = vsid ^ page;
    __u32 base = (hash & 0x3ff) << 3;
    __u32 i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) || ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        __u32 base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) || ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n Interrupt vector number.
 * @param istate Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    __address badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
            case AS_PF_FAULT:
                goto fail;
                break;
            case AS_PF_DEFER:
                /*
                 * The page fault came during copy_from_uspace()
                 * or copy_to_uspace().
                 */
                page_table_unlock(as, lock);
                return;
            default:
                panic("Unexpected pfrc (%d)\n", pfrc);
        }
    }
   
    pte->a = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte->pfn);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n Interrupt vector number.
 * @param istate Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    __address badvaddr;
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
   
    __u32 physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbia\n"
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    __u32 sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    __u32 i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        __u32 tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    __u32 sr;
   
    for (sr = 0; sr < 16; sr++) {
        __u32 vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");
    }
   
    __u32 upper;
    __u32 lower;
    __u32 mask;
    __u32 length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 1743	Rev 1758
1	/*	1	/*
2	* Copyright (C) 2006 Martin Decky	2	* Copyright (C) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39	#include <arch.h>	39	#include <arch.h>
40	#include <print.h>	40	#include <print.h>
41	#include <symtab.h>	41	#include <symtab.h>
42		42
43		43
44	/** Try to find PTE for faulting address	44	/** Try to find PTE for faulting address
45	*	45	*
46	* Try to find PTE for faulting address.	46	* Try to find PTE for faulting address.
47	* The as->lock must be held on entry to this function	47	* The as->lock must be held on entry to this function
48	* if lock is true.	48	* if lock is true.
49	*	49	*
50	* @param as Address space.	50	* @param as Address space.
51	* @param lock Lock/unlock the address space.	51	* @param lock Lock/unlock the address space.
52	* @param badvaddr Faulting virtual address.	52	* @param badvaddr Faulting virtual address.
53	* @param access Access mode that caused the fault.	53	* @param access Access mode that caused the fault.
54	* @param istate Pointer to interrupted state.	54	* @param istate Pointer to interrupted state.
55	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	55	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
56	* @return PTE on success, NULL otherwise.	56	* @return PTE on success, NULL otherwise.
57	*	57	*
58	*/	58	*/
59	static pte_t find_mapping_and_check(as_t as, bool lock, __address badvaddr, int access, istate_t istate, int pfrc)	59	static pte_t find_mapping_and_check(as_t as, bool lock, __address badvaddr, int access, istate_t istate, int pfrc)
60	{	60	{
61	/*	61	/*
62	* Check if the mapping exists in page tables.	62	* Check if the mapping exists in page tables.
63	*/	63	*/
64	pte_t *pte = page_mapping_find(as, badvaddr);	64	pte_t *pte = page_mapping_find(as, badvaddr);
65	if ((pte) && (pte->p)) {	65	if ((pte) && (pte->p)) {
66	/*	66	/*
67	* Mapping found in page tables.	67	* Mapping found in page tables.
68	* Immediately succeed.	68	* Immediately succeed.
69	*/	69	*/
70	return pte;	70	return pte;
71	} else {	71	} else {
72	int rc;	72	int rc;
73		73
74	/*	74	/*
75	* Mapping not found in page tables.	75	* Mapping not found in page tables.
76	* Resort to higher-level page fault handler.	76	* Resort to higher-level page fault handler.
77	*/	77	*/
78	page_table_unlock(as, lock);	78	page_table_unlock(as, lock);
79	switch (rc = as_page_fault(badvaddr, access, istate)) {	79	switch (rc = as_page_fault(badvaddr, access, istate)) {
80	case AS_PF_OK:	80	case AS_PF_OK:
81	/*	81	/*
82	* The higher-level page fault handler succeeded,	82	* The higher-level page fault handler succeeded,
83	* The mapping ought to be in place.	83	* The mapping ought to be in place.
84	*/	84	*/
85	page_table_lock(as, lock);	85	page_table_lock(as, lock);
86	pte = page_mapping_find(as, badvaddr);	86	pte = page_mapping_find(as, badvaddr);
87	ASSERT((pte) && (pte->p));	87	ASSERT((pte) && (pte->p));
88	*pfrc = 0;	88	*pfrc = 0;
89	return pte;	89	return pte;
90	case AS_PF_DEFER:	90	case AS_PF_DEFER:
91	page_table_lock(as, lock);	91	page_table_lock(as, lock);
92	*pfrc = rc;	92	*pfrc = rc;
93	return NULL;	93	return NULL;
94	case AS_PF_FAULT:	94	case AS_PF_FAULT:
95	page_table_lock(as, lock);	95	page_table_lock(as, lock);
96	printf("Page fault.\n");	96	printf("Page fault.\n");
97	*pfrc = rc;	97	*pfrc = rc;
98	return NULL;	98	return NULL;
99	default:	99	default:
100	panic("unexpected rc (%d)\n", rc);	100	panic("unexpected rc (%d)\n", rc);
101	}	101	}
102	}	102	}
103	}	103	}
104		104
105		105
106	static void pht_refill_fail(__address badvaddr, istate_t *istate)	106	static void pht_refill_fail(__address badvaddr, istate_t *istate)
107	{	107	{
108	char *symbol = "";	108	char *symbol = "";
109	char *sym2 = "";	109	char *sym2 = "";
110		110
111	char *s = get_symtab_entry(istate->pc);	111	char *s = get_symtab_entry(istate->pc);
112	if (s)	112	if (s)
113	symbol = s;	113	symbol = s;
114	s = get_symtab_entry(istate->lr);	114	s = get_symtab_entry(istate->lr);
115	if (s)	115	if (s)
116	sym2 = s;	116	sym2 = s;
117	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);	117	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
118	}	118	}
119		119
120		120
121	static void pht_insert(const __address vaddr, const pfn_t pfn)	121	static void pht_insert(const __address vaddr, const pfn_t pfn)
122	{	122	{
123	__u32 page = (vaddr >> 12) & 0xffff;	123	__u32 page = (vaddr >> 12) & 0xffff;
124	__u32 api = (vaddr >> 22) & 0x3f;	124	__u32 api = (vaddr >> 22) & 0x3f;
125		125
126	__u32 vsid;	126	__u32 vsid;
127	asm volatile (	127	asm volatile (
128	"mfsrin %0, %1\n"	128	"mfsrin %0, %1\n"
129	: "=r" (vsid)	129	: "=r" (vsid)
130	: "r" (vaddr)	130	: "r" (vaddr)
131	);	131	);
132		132
133	__u32 sdr1;	133	__u32 sdr1;
134	asm volatile (	134	asm volatile (
135	"mfsdr1 %0\n"	135	"mfsdr1 %0\n"
136	: "=r" (sdr1)	136	: "=r" (sdr1)
137	);	137	);
138	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	138	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
139		139
140	/* Primary hash (xor) */	140	/* Primary hash (xor) */
141	__u32 h = 0;	141	__u32 h = 0;
142	__u32 hash = vsid ^ page;	142	__u32 hash = vsid ^ page;
143	__u32 base = (hash & 0x3ff) << 3;	143	__u32 base = (hash & 0x3ff) << 3;
144	__u32 i;	144	__u32 i;
145	bool found = false;	145	bool found = false;
146		146
147	/* Find unused or colliding	147	/* Find unused or colliding
148	PTE in PTEG */	148	PTE in PTEG */
149	for (i = 0; i < 8; i++) {	149	for (i = 0; i < 8; i++) {
150	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {	150	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
151	found = true;	151	found = true;
152	break;	152	break;
153	}	153	}
154	}	154	}
155		155
156	if (!found) {	156	if (!found) {
157	/* Secondary hash (not) */	157	/* Secondary hash (not) */
158	__u32 base2 = (~hash & 0x3ff) << 3;	158	__u32 base2 = (~hash & 0x3ff) << 3;
159		159
160	/* Find unused or colliding	160	/* Find unused or colliding
161	PTE in PTEG */	161	PTE in PTEG */
162	for (i = 0; i < 8; i++) {	162	for (i = 0; i < 8; i++) {
163	if ((!phte[base2 + i].v) \|\| ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {	163	if ((!phte[base2 + i].v) \|\| ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
164	found = true;	164	found = true;
165	base = base2;	165	base = base2;
166	h = 1;	166	h = 1;
167	break;	167	break;
168	}	168	}
169	}	169	}
170		170
171	if (!found) {	171	if (!found) {
172	// TODO: A/C precedence groups	172	// TODO: A/C precedence groups
173	i = page % 8;	173	i = page % 8;
174	}	174	}
175	}	175	}
176		176
177	phte[base + i].v = 1;	177	phte[base + i].v = 1;
178	phte[base + i].vsid = vsid;	178	phte[base + i].vsid = vsid;
179	phte[base + i].h = h;	179	phte[base + i].h = h;
180	phte[base + i].api = api;	180	phte[base + i].api = api;
181	phte[base + i].rpn = pfn;	181	phte[base + i].rpn = pfn;
182	phte[base + i].r = 0;	182	phte[base + i].r = 0;
183	phte[base + i].c = 0;	183	phte[base + i].c = 0;
184	phte[base + i].pp = 2; // FIXME	184	phte[base + i].pp = 2; // FIXME
185	}	185	}
186		186
187		187
188	static void pht_real_insert(const __address vaddr, const pfn_t pfn)	188	static void pht_real_insert(const __address vaddr, const pfn_t pfn)
189	{	189	{
190	__u32 page = (vaddr >> 12) & 0xffff;	190	__u32 page = (vaddr >> 12) & 0xffff;
191	__u32 api = (vaddr >> 22) & 0x3f;	191	__u32 api = (vaddr >> 22) & 0x3f;
192		192
193	__u32 vsid;	193	__u32 vsid;
194	asm volatile (	194	asm volatile (
195	"mfsrin %0, %1\n"	195	"mfsrin %0, %1\n"
196	: "=r" (vsid)	196	: "=r" (vsid)
197	: "r" (vaddr)	197	: "r" (vaddr)
198	);	198	);
199		199
200	__u32 sdr1;	200	__u32 sdr1;
201	asm volatile (	201	asm volatile (
202	"mfsdr1 %0\n"	202	"mfsdr1 %0\n"
203	: "=r" (sdr1)	203	: "=r" (sdr1)
204	);	204	);
205	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	205	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
206		206
207	/* Primary hash (xor) */	207	/* Primary hash (xor) */
208	__u32 h = 0;	208	__u32 h = 0;
209	__u32 hash = vsid ^ page;	209	__u32 hash = vsid ^ page;
210	__u32 base = (hash & 0x3ff) << 3;	210	__u32 base = (hash & 0x3ff) << 3;
211	__u32 i;	211	__u32 i;
212	bool found = false;	212	bool found = false;
213		213
214	/* Find unused or colliding	214	/* Find unused or colliding
215	PTE in PTEG */	215	PTE in PTEG */
216	for (i = 0; i < 8; i++) {	216	for (i = 0; i < 8; i++) {
217	if ((!phte_physical[base + i].v) \|\| ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {	217	if ((!phte_physical[base + i].v) \|\| ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {
218	found = true;	218	found = true;
219	break;	219	break;
220	}	220	}
221	}	221	}
222		222
223	if (!found) {	223	if (!found) {
224	/* Secondary hash (not) */	224	/* Secondary hash (not) */
225	__u32 base2 = (~hash & 0x3ff) << 3;	225	__u32 base2 = (~hash & 0x3ff) << 3;
226		226
227	/* Find unused or colliding	227	/* Find unused or colliding
228	PTE in PTEG */	228	PTE in PTEG */
229	for (i = 0; i < 8; i++) {	229	for (i = 0; i < 8; i++) {
230	if ((!phte_physical[base2 + i].v) \|\| ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {	230	if ((!phte_physical[base2 + i].v) \|\| ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {
231	found = true;	231	found = true;
232	base = base2;	232	base = base2;
233	h = 1;	233	h = 1;
234	break;	234	break;
235	}	235	}
236	}	236	}
237		237
238	if (!found) {	238	if (!found) {
239	// TODO: A/C precedence groups	239	// TODO: A/C precedence groups
240	i = page % 8;	240	i = page % 8;
241	}	241	}
242	}	242	}
243		243
244	phte_physical[base + i].v = 1;	244	phte_physical[base + i].v = 1;
245	phte_physical[base + i].vsid = vsid;	245	phte_physical[base + i].vsid = vsid;
246	phte_physical[base + i].h = h;	246	phte_physical[base + i].h = h;
247	phte_physical[base + i].api = api;	247	phte_physical[base + i].api = api;
248	phte_physical[base + i].rpn = pfn;	248	phte_physical[base + i].rpn = pfn;
249	phte_physical[base + i].r = 0;	249	phte_physical[base + i].r = 0;
250	phte_physical[base + i].c = 0;	250	phte_physical[base + i].c = 0;
251	phte_physical[base + i].pp = 2; // FIXME	251	phte_physical[base + i].pp = 2; // FIXME
252	}	252	}
253		253
254		254
255	/** Process Instruction/Data Storage Interrupt	255	/** Process Instruction/Data Storage Interrupt
256	*	256	*
257	* @param n Interrupt vector number.	257	* @param n Interrupt vector number.
258	* @param istate Interrupted register context.	258	* @param istate Interrupted register context.
259	*	259	*
260	*/	260	*/
261	void pht_refill(int n, istate_t *istate)	261	void pht_refill(int n, istate_t *istate)
262	{	262	{
263	__address badvaddr;	263	__address badvaddr;
264	pte_t *pte;	264	pte_t *pte;
265	int pfrc;	265	int pfrc;
266	as_t *as;	266	as_t *as;
267	bool lock;	267	bool lock;
268		268
269	if (AS == NULL) {	269	if (AS == NULL) {
270	as = AS_KERNEL;	270	as = AS_KERNEL;
271	lock = false;	271	lock = false;
272	} else {	272	} else {
273	as = AS;	273	as = AS;
274	lock = true;	274	lock = true;
275	}	275	}
276		276
277	if (n == VECTOR_DATA_STORAGE) {	277	if (n == VECTOR_DATA_STORAGE) {
278	asm volatile (	278	asm volatile (
279	"mfdar %0\n"	279	"mfdar %0\n"
280	: "=r" (badvaddr)	280	: "=r" (badvaddr)
281	);	281	);
282	} else	282	} else
283	badvaddr = istate->pc;	283	badvaddr = istate->pc;
284		284
285	page_table_lock(as, lock);	285	page_table_lock(as, lock);
286		286
287	pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);	287	pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
288	if (!pte) {	288	if (!pte) {
289	switch (pfrc) {	289	switch (pfrc) {
290	case AS_PF_FAULT:	290	case AS_PF_FAULT:
291	goto fail;	291	goto fail;
292	break;	292	break;
293	case AS_PF_DEFER:	293	case AS_PF_DEFER:
294	/*	294	/*
295	* The page fault came during copy_from_uspace()	295	* The page fault came during copy_from_uspace()
296	* or copy_to_uspace().	296	* or copy_to_uspace().
297	*/	297	*/
298	page_table_unlock(as, lock);	298	page_table_unlock(as, lock);
299	return;	299	return;
300	default:	300	default:
301	panic("Unexpected pfrc (%d)\n", pfrc);	301	panic("Unexpected pfrc (%d)\n", pfrc);
302	}	302	}
303	}	303	}
304		304
305	pte->a = 1; /* Record access to PTE */	305	pte->a = 1; /* Record access to PTE */
306	pht_insert(badvaddr, pte->pfn);	306	pht_insert(badvaddr, pte->pfn);
307		307
308	page_table_unlock(as, lock);	308	page_table_unlock(as, lock);
309	return;	309	return;
310		310
311	fail:	311	fail:
312	page_table_unlock(as, lock);	312	page_table_unlock(as, lock);
313	pht_refill_fail(badvaddr, istate);	313	pht_refill_fail(badvaddr, istate);
314	}	314	}
315		315
316		316
317	/** Process Instruction/Data Storage Interrupt in Real Mode	317	/** Process Instruction/Data Storage Interrupt in Real Mode
318	*	318	*
319	* @param n Interrupt vector number.	319	* @param n Interrupt vector number.
320	* @param istate Interrupted register context.	320	* @param istate Interrupted register context.
321	*	321	*
322	*/	322	*/
323	bool pht_real_refill(int n, istate_t *istate)	323	bool pht_real_refill(int n, istate_t *istate)
324	{	324	{
325	__address badvaddr;	325	__address badvaddr;
326		326
327	if (n == VECTOR_DATA_STORAGE) {	327	if (n == VECTOR_DATA_STORAGE) {
328	asm volatile (	328	asm volatile (
329	"mfdar %0\n"	329	"mfdar %0\n"
330	: "=r" (badvaddr)	330	: "=r" (badvaddr)
331	);	331	);
332	} else	332	} else
333	badvaddr = istate->pc;	333	badvaddr = istate->pc;
334		334
335	__u32 physmem;	335	__u32 physmem;
336	asm volatile (	336	asm volatile (
337	"mfsprg3 %0\n"	337	"mfsprg3 %0\n"
338	: "=r" (physmem)	338	: "=r" (physmem)
339	);	339	);
340		340
341	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	341	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
342	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	342	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
343	return true;	343	return true;
344	}	344	}
345		345
346	return false;	346	return false;
347	}	347	}
348		348
349		349
350	void tlb_arch_init(void)	350	void tlb_arch_init(void)
351	{	351	{
352	tlb_invalidate_all();	352	tlb_invalidate_all();
353	}	353	}
354		354
355		355
356	void tlb_invalidate_all(void)	356	void tlb_invalidate_all(void)
357	{	357	{
358	asm volatile (	358	asm volatile (
359	"tlbia\n"	359	"tlbia\n"
360	"tlbsync\n"	360	"tlbsync\n"
361	);	361	);
362	}	362	}
363		363
364		364
365	void tlb_invalidate_asid(asid_t asid)	365	void tlb_invalidate_asid(asid_t asid)
366	{	366	{
-		367	__u32 sdr1;
-		368	asm volatile (
-		369	"mfsdr1 %0\n"
-		370	: "=r" (sdr1)
-		371	);
-		372	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
-		373
367	// TODO	374	__u32 i;
-		375	for (i = 0; i < 8192; i++) {
-		376	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && (phte[i].vsid < ((asid << 4) + 16)))
-		377	phte[i].v = 0;
-		378	}
368	tlb_invalidate_all();	379	tlb_invalidate_all();
369	}	380	}
370		381
371		382
372	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	383	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
373	{	384	{
374	// TODO	385	// TODO
375	tlb_invalidate_all();	386	tlb_invalidate_all();
376	}	387	}
377		388
378		389
379	#define PRINT_BAT(name, ureg, lreg) \	390	#define PRINT_BAT(name, ureg, lreg) \
380	asm volatile ( \	391	asm volatile ( \
381	"mfspr %0," #ureg "\n" \	392	"mfspr %0," #ureg "\n" \
382	"mfspr %1," #lreg "\n" \	393	"mfspr %1," #lreg "\n" \
383	: "=r" (upper), "=r" (lower) \	394	: "=r" (upper), "=r" (lower) \
384	); \	395	); \
385	mask = (upper & 0x1ffc) >> 2; \	396	mask = (upper & 0x1ffc) >> 2; \
386	if (upper & 3) { \	397	if (upper & 3) { \
387	__u32 tmp = mask; \	398	__u32 tmp = mask; \
388	length = 128; \	399	length = 128; \
389	while (tmp) { \	400	while (tmp) { \
390	if ((tmp & 1) == 0) { \	401	if ((tmp & 1) == 0) { \
391	printf("ibat[0]: error in mask\n"); \	402	printf("ibat[0]: error in mask\n"); \
392	break; \	403	break; \
393	} \	404	} \
394	length <<= 1; \	405	length <<= 1; \
395	tmp >>= 1; \	406	tmp >>= 1; \
396	} \	407	} \
397	} else \	408	} else \
398	length = 0; \	409	length = 0; \
399	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");	410	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");
400		411
401		412
402	void tlb_print(void)	413	void tlb_print(void)
403	{	414	{
404	__u32 sr;	415	__u32 sr;
405		416
406	for (sr = 0; sr < 16; sr++) {	417	for (sr = 0; sr < 16; sr++) {
407	__u32 vsid;	418	__u32 vsid;
408	asm volatile (	419	asm volatile (
409	"mfsrin %0, %1\n"	420	"mfsrin %0, %1\n"
410	: "=r" (vsid)	421	: "=r" (vsid)
411	: "r" (sr << 28)	422	: "r" (sr << 28)
412	);	423	);
413	printf("vsid[%d]: VSID=%.p (ASID=%d)%s%s\n", sr, sizeof(vsid) 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");	424	printf("vsid[%d]: VSID=%.p (ASID=%d)%s%s\n", sr, sizeof(vsid) 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");
414	}	425	}
415		426
416	__u32 upper;	427	__u32 upper;
417	__u32 lower;	428	__u32 lower;
418	__u32 mask;	429	__u32 mask;
419	__u32 length;	430	__u32 length;
420		431
421	PRINT_BAT("ibat[0]", 528, 529);	432	PRINT_BAT("ibat[0]", 528, 529);
422	PRINT_BAT("ibat[1]", 530, 531);	433	PRINT_BAT("ibat[1]", 530, 531);
423	PRINT_BAT("ibat[2]", 532, 533);	434	PRINT_BAT("ibat[2]", 532, 533);
424	PRINT_BAT("ibat[3]", 534, 535);	435	PRINT_BAT("ibat[3]", 534, 535);
425		436
426	PRINT_BAT("dbat[0]", 536, 537);	437	PRINT_BAT("dbat[0]", 536, 537);
427	PRINT_BAT("dbat[1]", 538, 539);	438	PRINT_BAT("dbat[1]", 538, 539);
428	PRINT_BAT("dbat[2]", 540, 541);	439	PRINT_BAT("dbat[2]", 540, 541);
429	PRINT_BAT("dbat[3]", 542, 543);	440	PRINT_BAT("dbat[3]", 542, 543);
430	}	441	}
431		442
432	/** @}	443	/** @}
433	*/	444	*/
434		445

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(root)/kernel/trunk/arch/ppc32/src/mm/tlb.c – Rev 1743 → 1758