WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (C) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as       Address space.
 * @param lock     Lock/unlock the address space.
 * @param badvaddr Faulting virtual address.
 * @param access   Access mode that caused the fault.
 * @param istate   Pointer to interrupted state.
 * @param pfrc     Pointer to variable where as_page_fault() return code will be stored.
 * @return         PTE on success, NULL otherwise.
 *
 */
static pte_t *find_mapping_and_check(as_t *as, bool lock, __address badvaddr, int access, istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->p)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
            case AS_PF_OK:
                /*
                 * The higher-level page fault handler succeeded,
                 * The mapping ought to be in place.
                 */
                page_table_lock(as, lock);
                pte = page_mapping_find(as, badvaddr);
                ASSERT((pte) && (pte->p));
                return pte;
            case AS_PF_DEFER:
                page_table_lock(as, lock);
                *pfrc = rc;
                return NULL;
            case AS_PF_FAULT:
                page_table_lock(as, lock);
                printf("Page fault.\n");
                *pfrc = rc;
                return NULL;
            default:
                panic("unexpected rc (%d)\n", rc);
        }  
    }
}
 
 
static void pht_refill_fail(__address badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->pc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->lr);
    if (s)
        sym2 = s;
    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const __address vaddr, const pfn_t pfn)
{
    __u32 page = (vaddr >> 12) & 0xffff;
    __u32 api = (vaddr >> 22) & 0x3f;
   
    __u32 vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    __u32 sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    __u32 h = 0;
    __u32 hash = vsid ^ page;
    __u32 base = (hash & 0x3ff) << 3;
    __u32 i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        __u32 base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const __address vaddr, const pfn_t pfn)
{
    __u32 page = (vaddr >> 12) & 0xffff;
    __u32 api = (vaddr >> 22) & 0x3f;
   
    __u32 vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    __u32 sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    __u32 h = 0;
    __u32 hash = vsid ^ page;
    __u32 base = (hash & 0x3ff) << 3;
    __u32 i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) || ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        __u32 base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) || ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n Interrupt vector number.
 * @param istate Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    __address badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
            case AS_PF_FAULT:
                goto fail;
                break;
            case AS_PF_DEFER:
                /*
                 * The page fault came during copy_from_uspace()
                 * or copy_to_uspace().
                 */
                page_table_unlock(as, lock);
                return;
            default:
                panic("Unexpected pfrc (%d)\n", pfrc);
        }
    }
   
    pte->a = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte->pfn);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n Interrupt vector number.
 * @param istate Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    __address badvaddr;
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
   
    __u32 physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbia\n"
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    // TODO
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        __u32 tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    __u32 sr;
   
    for (sr = 0; sr < 16; sr++) {
        __u32 vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");
    }
   
    __u32 upper;
    __u32 lower;
    __u32 mask;
    __u32 length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 1733	Rev 1736
1	/*	1	/*
2	* Copyright (C) 2006 Martin Decky	2	* Copyright (C) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39	#include <arch.h>	39	#include <arch.h>
40	#include <print.h>	40	#include <print.h>
41	#include <symtab.h>	41	#include <symtab.h>
42		42
43		43
44	/** Try to find PTE for faulting address	44	/** Try to find PTE for faulting address
45	*	45	*
46	* Try to find PTE for faulting address.	46	* Try to find PTE for faulting address.
47	* The as->lock must be held on entry to this function	47	* The as->lock must be held on entry to this function
48	* if lock is true.	48	* if lock is true.
49	*	49	*
50	* @param as Address space.	50	* @param as Address space.
51	* @param lock Lock/unlock the address space.	51	* @param lock Lock/unlock the address space.
52	* @param badvaddr Faulting virtual address.	52	* @param badvaddr Faulting virtual address.
53	* @param access Access mode that caused the fault.	53	* @param access Access mode that caused the fault.
54	* @param istate Pointer to interrupted state.	54	* @param istate Pointer to interrupted state.
55	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	55	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
56	* @return PTE on success, NULL otherwise.	56	* @return PTE on success, NULL otherwise.
57	*	57	*
58	*/	58	*/
59	static pte_t find_mapping_and_check(as_t as, bool lock, __address badvaddr, int access, istate_t istate, int pfrc)	59	static pte_t find_mapping_and_check(as_t as, bool lock, __address badvaddr, int access, istate_t istate, int pfrc)
60	{	60	{
61	/*	61	/*
62	* Check if the mapping exists in page tables.	62	* Check if the mapping exists in page tables.
63	*/	63	*/
64	pte_t *pte = page_mapping_find(as, badvaddr);	64	pte_t *pte = page_mapping_find(as, badvaddr);
65	if ((pte) && (pte->p)) {	65	if ((pte) && (pte->p)) {
66	/*	66	/*
67	* Mapping found in page tables.	67	* Mapping found in page tables.
68	* Immediately succeed.	68	* Immediately succeed.
69	*/	69	*/
70	return pte;	70	return pte;
71	} else {	71	} else {
72	int rc;	72	int rc;
73		73
74	/*	74	/*
75	* Mapping not found in page tables.	75	* Mapping not found in page tables.
76	* Resort to higher-level page fault handler.	76	* Resort to higher-level page fault handler.
77	*/	77	*/
78	page_table_unlock(as, lock);	78	page_table_unlock(as, lock);
79	switch (rc = as_page_fault(badvaddr, access, istate)) {	79	switch (rc = as_page_fault(badvaddr, access, istate)) {
80	case AS_PF_OK:	80	case AS_PF_OK:
81	/*	81	/*
82	* The higher-level page fault handler succeeded,	82	* The higher-level page fault handler succeeded,
83	* The mapping ought to be in place.	83	* The mapping ought to be in place.
84	*/	84	*/
85	page_table_lock(as, lock);	85	page_table_lock(as, lock);
86	pte = page_mapping_find(as, badvaddr);	86	pte = page_mapping_find(as, badvaddr);
87	ASSERT((pte) && (pte->p));	87	ASSERT((pte) && (pte->p));
88	return pte;	88	return pte;
89	case AS_PF_DEFER:	89	case AS_PF_DEFER:
90	page_table_lock(as, lock);	90	page_table_lock(as, lock);
91	*pfrc = rc;	91	*pfrc = rc;
92	return NULL;	92	return NULL;
93	case AS_PF_FAULT:	93	case AS_PF_FAULT:
94	page_table_lock(as, lock);	94	page_table_lock(as, lock);
95	printf("Page fault.\n");	95	printf("Page fault.\n");
96	*pfrc = rc;	96	*pfrc = rc;
97	return NULL;	97	return NULL;
98	default:	98	default:
99	panic("unexpected rc (%d)\n", rc);	99	panic("unexpected rc (%d)\n", rc);
100	}	100	}
101	}	101	}
102	}	102	}
103		103
104		104
105	static void pht_refill_fail(__address badvaddr, istate_t *istate)	105	static void pht_refill_fail(__address badvaddr, istate_t *istate)
106	{	106	{
107	char *symbol = "";	107	char *symbol = "";
108	char *sym2 = "";	108	char *sym2 = "";
109		109
110	char *s = get_symtab_entry(istate->pc);	110	char *s = get_symtab_entry(istate->pc);
111	if (s)	111	if (s)
112	symbol = s;	112	symbol = s;
113	s = get_symtab_entry(istate->lr);	113	s = get_symtab_entry(istate->lr);
114	if (s)	114	if (s)
115	sym2 = s;	115	sym2 = s;
116	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);	116	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
117	}	117	}
118		118
119		119
120	static void pht_insert(const __address vaddr, const pfn_t pfn)	120	static void pht_insert(const __address vaddr, const pfn_t pfn)
121	{	121	{
122	__u32 page = (vaddr >> 12) & 0xffff;	122	__u32 page = (vaddr >> 12) & 0xffff;
123	__u32 api = (vaddr >> 22) & 0x3f;	123	__u32 api = (vaddr >> 22) & 0x3f;
124		124
125	__u32 vsid;	125	__u32 vsid;
126	asm volatile (	126	asm volatile (
127	"mfsrin %0, %1\n"	127	"mfsrin %0, %1\n"
128	: "=r" (vsid)	128	: "=r" (vsid)
129	: "r" (vaddr)	129	: "r" (vaddr)
130	);	130	);
131		131
132	__u32 sdr1;	132	__u32 sdr1;
133	asm volatile (	133	asm volatile (
134	"mfsdr1 %0\n"	134	"mfsdr1 %0\n"
135	: "=r" (sdr1)	135	: "=r" (sdr1)
136	);	136	);
137	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	137	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
138		138
139	/* Primary hash (xor) */	139	/* Primary hash (xor) */
140	__u32 h = 0;	140	__u32 h = 0;
141	__u32 hash = vsid ^ page;	141	__u32 hash = vsid ^ page;
142	__u32 base = (hash & 0x3ff) << 3;	142	__u32 base = (hash & 0x3ff) << 3;
143	__u32 i;	143	__u32 i;
144	bool found = false;	144	bool found = false;
145		145
146	/* Find unused or colliding	146	/* Find unused or colliding
147	PTE in PTEG */	147	PTE in PTEG */
148	for (i = 0; i < 8; i++) {	148	for (i = 0; i < 8; i++) {
149	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {	149	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
150	found = true;	150	found = true;
151	break;	151	break;
152	}	152	}
153	}	153	}
154		154
155	if (!found) {	155	if (!found) {
156	/* Secondary hash (not) */	156	/* Secondary hash (not) */
157	__u32 base2 = (~hash & 0x3ff) << 3;	157	__u32 base2 = (~hash & 0x3ff) << 3;
158		158
159	/* Find unused or colliding	159	/* Find unused or colliding
160	PTE in PTEG */	160	PTE in PTEG */
161	for (i = 0; i < 8; i++) {	161	for (i = 0; i < 8; i++) {
162	if ((!phte[base2 + i].v) \|\| ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {	162	if ((!phte[base2 + i].v) \|\| ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
163	found = true;	163	found = true;
164	base = base2;	164	base = base2;
165	h = 1;	165	h = 1;
166	break;	166	break;
167	}	167	}
168	}	168	}
169		169
170	if (!found) {	170	if (!found) {
171	// TODO: A/C precedence groups	171	// TODO: A/C precedence groups
172	i = page % 8;	172	i = page % 8;
173	}	173	}
174	}	174	}
175		175
176	phte[base + i].v = 1;	176	phte[base + i].v = 1;
177	phte[base + i].vsid = vsid;	177	phte[base + i].vsid = vsid;
178	phte[base + i].h = h;	178	phte[base + i].h = h;
179	phte[base + i].api = api;	179	phte[base + i].api = api;
180	phte[base + i].rpn = pfn;	180	phte[base + i].rpn = pfn;
181	phte[base + i].r = 0;	181	phte[base + i].r = 0;
182	phte[base + i].c = 0;	182	phte[base + i].c = 0;
183	phte[base + i].pp = 2; // FIXME	183	phte[base + i].pp = 2; // FIXME
184	}	184	}
185		185
186		186
187	static void pht_real_insert(const __address vaddr, const pfn_t pfn)	187	static void pht_real_insert(const __address vaddr, const pfn_t pfn)
188	{	188	{
189	__u32 page = (vaddr >> 12) & 0xffff;	189	__u32 page = (vaddr >> 12) & 0xffff;
190	__u32 api = (vaddr >> 22) & 0x3f;	190	__u32 api = (vaddr >> 22) & 0x3f;
191		191
192	__u32 vsid;	192	__u32 vsid;
193	asm volatile (	193	asm volatile (
194	"mfsrin %0, %1\n"	194	"mfsrin %0, %1\n"
195	: "=r" (vsid)	195	: "=r" (vsid)
196	: "r" (vaddr)	196	: "r" (vaddr)
197	);	197	);
198		198
199	__u32 sdr1;	199	__u32 sdr1;
200	asm volatile (	200	asm volatile (
201	"mfsdr1 %0\n"	201	"mfsdr1 %0\n"
202	: "=r" (sdr1)	202	: "=r" (sdr1)
203	);	203	);
204	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	204	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
205		205
206	/* Primary hash (xor) */	206	/* Primary hash (xor) */
207	__u32 h = 0;	207	__u32 h = 0;
208	__u32 hash = vsid ^ page;	208	__u32 hash = vsid ^ page;
209	__u32 base = (hash & 0x3ff) << 3;	209	__u32 base = (hash & 0x3ff) << 3;
210	__u32 i;	210	__u32 i;
211	bool found = false;	211	bool found = false;
212		212
213	/* Find unused or colliding	213	/* Find unused or colliding
214	PTE in PTEG */	214	PTE in PTEG */
215	for (i = 0; i < 8; i++) {	215	for (i = 0; i < 8; i++) {
216	if ((!phte_physical[base + i].v) \|\| ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {	216	if ((!phte_physical[base + i].v) \|\| ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {
217	found = true;	217	found = true;
218	break;	218	break;
219	}	219	}
220	}	220	}
221		221
222	if (!found) {	222	if (!found) {
223	/* Secondary hash (not) */	223	/* Secondary hash (not) */
224	__u32 base2 = (~hash & 0x3ff) << 3;	224	__u32 base2 = (~hash & 0x3ff) << 3;
225		225
226	/* Find unused or colliding	226	/* Find unused or colliding
227	PTE in PTEG */	227	PTE in PTEG */
228	for (i = 0; i < 8; i++) {	228	for (i = 0; i < 8; i++) {
229	if ((!phte_physical[base2 + i].v) \|\| ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {	229	if ((!phte_physical[base2 + i].v) \|\| ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {
230	found = true;	230	found = true;
231	base = base2;	231	base = base2;
232	h = 1;	232	h = 1;
233	break;	233	break;
234	}	234	}
235	}	235	}
236		236
237	if (!found) {	237	if (!found) {
238	// TODO: A/C precedence groups	238	// TODO: A/C precedence groups
239	i = page % 8;	239	i = page % 8;
240	}	240	}
241	}	241	}
242		242
243	phte_physical[base + i].v = 1;	243	phte_physical[base + i].v = 1;
244	phte_physical[base + i].vsid = vsid;	244	phte_physical[base + i].vsid = vsid;
245	phte_physical[base + i].h = h;	245	phte_physical[base + i].h = h;
246	phte_physical[base + i].api = api;	246	phte_physical[base + i].api = api;
247	phte_physical[base + i].rpn = pfn;	247	phte_physical[base + i].rpn = pfn;
248	phte_physical[base + i].r = 0;	248	phte_physical[base + i].r = 0;
249	phte_physical[base + i].c = 0;	249	phte_physical[base + i].c = 0;
250	phte_physical[base + i].pp = 2; // FIXME	250	phte_physical[base + i].pp = 2; // FIXME
251	}	251	}
252		252
253		253
254	/** Process Instruction/Data Storage Interrupt	254	/** Process Instruction/Data Storage Interrupt
255	*	255	*
256	* @param n Interrupt vector number.	256	* @param n Interrupt vector number.
257	* @param istate Interrupted register context.	257	* @param istate Interrupted register context.
258	*	258	*
259	*/	259	*/
260	void pht_refill(int n, istate_t *istate)	260	void pht_refill(int n, istate_t *istate)
261	{	261	{
262	__address badvaddr;	262	__address badvaddr;
263	pte_t *pte;	263	pte_t *pte;
264	int pfrc;	264	int pfrc;
265	as_t *as;	265	as_t *as;
266	bool lock;	266	bool lock;
267		267
268	if (AS == NULL) {	268	if (AS == NULL) {
269	as = AS_KERNEL;	269	as = AS_KERNEL;
270	lock = false;	270	lock = false;
271	} else {	271	} else {
272	as = AS;	272	as = AS;
273	lock = true;	273	lock = true;
274	}	274	}
275		275
276	if (n == VECTOR_DATA_STORAGE) {	276	if (n == VECTOR_DATA_STORAGE) {
277	asm volatile (	277	asm volatile (
278	"mfdar %0\n"	278	"mfdar %0\n"
279	: "=r" (badvaddr)	279	: "=r" (badvaddr)
280	);	280	);
281	} else	281	} else
282	badvaddr = istate->pc;	282	badvaddr = istate->pc;
283		283
284	page_table_lock(as, lock);	284	page_table_lock(as, lock);
285		285
286	pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);	286	pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
287	if (!pte) {	287	if (!pte) {
288	switch (pfrc) {	288	switch (pfrc) {
289	case AS_PF_FAULT:	289	case AS_PF_FAULT:
290	goto fail;	290	goto fail;
291	break;	291	break;
292	case AS_PF_DEFER:	292	case AS_PF_DEFER:
293	/*	293	/*
294	* The page fault came during copy_from_uspace()	294	* The page fault came during copy_from_uspace()
295	* or copy_to_uspace().	295	* or copy_to_uspace().
296	*/	296	*/
297	page_table_unlock(as, lock);	297	page_table_unlock(as, lock);
298	return;	298	return;
299	default:	299	default:
300	panic("Unexpected pfrc (%d)\n", pfrc);	300	panic("Unexpected pfrc (%d)\n", pfrc);
301	}	301	}
302	}	302	}
303		303
304	pte->a = 1; /* Record access to PTE */	304	pte->a = 1; /* Record access to PTE */
305	pht_insert(badvaddr, pte->pfn);	305	pht_insert(badvaddr, pte->pfn);
306		306
307	page_table_unlock(as, lock);	307	page_table_unlock(as, lock);
308	return;	308	return;
309		309
310	fail:	310	fail:
311	page_table_unlock(as, lock);	311	page_table_unlock(as, lock);
312	pht_refill_fail(badvaddr, istate);	312	pht_refill_fail(badvaddr, istate);
313	}	313	}
314		314
315		315
316	/** Process Instruction/Data Storage Interrupt in Real Mode	316	/** Process Instruction/Data Storage Interrupt in Real Mode
317	*	317	*
318	* @param n Interrupt vector number.	318	* @param n Interrupt vector number.
319	* @param istate Interrupted register context.	319	* @param istate Interrupted register context.
320	*	320	*
321	*/	321	*/
322	bool pht_real_refill(int n, istate_t *istate)	322	bool pht_real_refill(int n, istate_t *istate)
323	{	323	{
324	__address badvaddr;	324	__address badvaddr;
325		325
326	if (n == VECTOR_DATA_STORAGE) {	326	if (n == VECTOR_DATA_STORAGE) {
327	asm volatile (	327	asm volatile (
328	"mfdar %0\n"	328	"mfdar %0\n"
329	: "=r" (badvaddr)	329	: "=r" (badvaddr)
330	);	330	);
331	} else	331	} else
332	badvaddr = istate->pc;	332	badvaddr = istate->pc;
333		333
334	__u32 physmem;	334	__u32 physmem;
335	asm volatile (	335	asm volatile (
336	"mfsprg3 %0\n"	336	"mfsprg3 %0\n"
337	: "=r" (physmem)	337	: "=r" (physmem)
338	);	338	);
339		339
340	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	340	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
341	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	341	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
342	return true;	342	return true;
343	}	343	}
344		344
345	return false;	345	return false;
346	}	346	}
347		347
348		348
349	void tlb_arch_init(void)	349	void tlb_arch_init(void)
350	{	350	{
351	tlb_invalidate_all();	351	tlb_invalidate_all();
352	}	352	}
353		353
354		354
355	void tlb_invalidate_all(void)	355	void tlb_invalidate_all(void)
356	{	356	{
357	asm volatile (	357	asm volatile (
358	"tlbia\n"	358	"tlbia\n"
359	"tlbsync\n"	359	"tlbsync\n"
360	);	360	);
361	}	361	}
362		362
363		363
364	void tlb_invalidate_asid(asid_t asid)	364	void tlb_invalidate_asid(asid_t asid)
365	{	365	{
366	// TODO	366	// TODO
367	tlb_invalidate_all();	367	tlb_invalidate_all();
368	}	368	}
369		369
370		370
371	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	371	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
372	{	372	{
373	// TODO	373	// TODO
374	tlb_invalidate_all();	374	tlb_invalidate_all();
375	}	375	}
376		376
377		377
-		378	#define PRINT_BAT(name, ureg, lreg) \
-		379	asm volatile ( \
-		380	"mfspr %0," #ureg "\n" \
-		381	"mfspr %1," #lreg "\n" \
-		382	: "=r" (upper), "=r" (lower) \
-		383	); \
-		384	mask = (upper & 0x1ffc) >> 2; \
-		385	if (upper & 3) { \
-		386	__u32 tmp = mask; \
-		387	length = 128; \
-		388	while (tmp) { \
-		389	if ((tmp & 1) == 0) { \
-		390	printf("ibat[0]: error in mask\n"); \
-		391	break; \
-		392	} \
-		393	length <<= 1; \
-		394	tmp >>= 1; \
-		395	} \
-		396	} else \
-		397	length = 0; \
-		398	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");
-		399
-		400
378	void tlb_print(void)	401	void tlb_print(void)
379	{	402	{
380	__u32 sr;	403	__u32 sr;
381		404
382	for (sr = 0; sr < 16; sr++) {	405	for (sr = 0; sr < 16; sr++) {
383	__u32 vsid;	406	__u32 vsid;
384	asm volatile (	407	asm volatile (
385	"mfsrin %0, %1\n"	408	"mfsrin %0, %1\n"
386	: "=r" (vsid)	409	: "=r" (vsid)
387	: "r" (sr << 28)	410	: "r" (sr << 28)
388	);	411	);
389	printf("vsid[%#x]=%#x\n", sr << 28, vsid);	412	printf("vsid[%d]: VSID=%.p (ASID=%d)%s%s\n", sr, sizeof(vsid) 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");
390	}	413	}
-		414
-		415	__u32 upper;
-		416	__u32 lower;
-		417	__u32 mask;
-		418	__u32 length;
-		419
-		420	PRINT_BAT("ibat[0]", 528, 529);
-		421	PRINT_BAT("ibat[1]", 530, 531);
-		422	PRINT_BAT("ibat[2]", 532, 533);
-		423	PRINT_BAT("ibat[3]", 534, 535);
-		424
-		425	PRINT_BAT("dbat[0]", 536, 537);
-		426	PRINT_BAT("dbat[1]", 538, 539);
-		427	PRINT_BAT("dbat[2]", 540, 541);
-		428	PRINT_BAT("dbat[3]", 542, 543);
391	}	429	}
392		430
393	/** @}	431	/** @}
394	*/	432	*/
395		433

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(root)/kernel/trunk/arch/ppc32/src/mm/tlb.c – Rev 1733 → 1736