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/*
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/*
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 * Copyright (C) 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup ppc32mm
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/** @addtogroup ppc32mm
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <arch/mm/as.h>
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#include <arch/mm/as.h>
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#include <genarch/mm/as_pt.h>
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#include <genarch/mm/as_pt.h>
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#include <genarch/mm/asid_fifo.h>
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#include <genarch/mm/asid_fifo.h>
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#include <arch.h>
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#include <arch.h>
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/** Architecture dependent address space init. */
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/** Architecture dependent address space init. */
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void as_arch_init(void)
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void as_arch_init(void)
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{
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{
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    as_operations = &as_pt_operations;
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    as_operations = &as_pt_operations;
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    asid_fifo_init();
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    asid_fifo_init();
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}
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}
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/** Install address space.
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/** Install address space.
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 *
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 *
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 * Install ASID.
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 * Install ASID.
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 *
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 *
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 * @param as Address space structure.
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 * @param as Address space structure.
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 *
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 *
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 */
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 */
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void as_install_arch(as_t *as)
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void as_install_arch(as_t *as)
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{
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{
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    asid_t asid;
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    asid_t asid;
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    ipl_t ipl;
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    ipl_t ipl;
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    __u32 sr;
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    uint32_t sr;
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    ipl = interrupts_disable();
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    ipl = interrupts_disable();
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    spinlock_lock(&as->lock);
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    spinlock_lock(&as->lock);
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    asid = as->asid;
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    asid = as->asid;
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    /* Lower 2 GB, user and supervisor access */
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    /* Lower 2 GB, user and supervisor access */
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    for (sr = 0; sr < 8; sr++) {
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    for (sr = 0; sr < 8; sr++) {
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        asm volatile (
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        asm volatile (
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            "mtsrin %0, %1\n"
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            "mtsrin %0, %1\n"
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            :
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            :
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            : "r" ((0x6000 << 16) + (asid << 4) + sr), "r" (sr << 28)
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            : "r" ((0x6000 << 16) + (asid << 4) + sr), "r" (sr << 28)
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        );
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        );
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    }
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    }
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    /* Upper 2 GB, only supervisor access */
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    /* Upper 2 GB, only supervisor access */
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    for (sr = 8; sr < 16; sr++) {
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    for (sr = 8; sr < 16; sr++) {
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        asm volatile (
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        asm volatile (
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            "mtsrin %0, %1\n"
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            "mtsrin %0, %1\n"
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            :
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            :
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            : "r" ((0x4000 << 16) + (asid << 4) + sr), "r" (sr << 28)
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            : "r" ((0x4000 << 16) + (asid << 4) + sr), "r" (sr << 28)
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        );
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        );
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    }
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    }
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    spinlock_unlock(&as->lock);
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    spinlock_unlock(&as->lock);
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    interrupts_restore(ipl);
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    interrupts_restore(ipl);
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}
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}
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/** @}
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/** @}
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 */
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 */
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