WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ppc32/src/asm.S


#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
 
.text
 
.global userspace_asm
.global iret
.global iret_syscall
.global invalidate_bat
.global memsetb
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
 
userspace_asm:
 
	# r3 = uspace_uarg
	# r4 = stack
	# r5 = entry
	
	# disable interrupts
 
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	# set entry point
	
	mtsrr0 r5
	
	# set problem state, enable interrupts
	
	ori r31, r31, msr_pr
	ori r31, r31, msr_ee
	mtsrr1 r31
	
	# set stack
	
	mr sp, r4
	
	# jump to userspace
	
	rfi
 
iret:
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r3, 16(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 152(sp)
	lwz sp, 156(sp)
	
	rfi
 
iret_syscall:
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 152(sp)
	lwz sp, 156(sp)
 
	rfi
	
invalidate_bat:
	
	# invalidate block address translation registers
	
	li r14, 0
	
	mtspr ibat0u, r14
	mtspr ibat0l, r14
	
	mtspr ibat1u, r14
	mtspr ibat1l, r14
	
	mtspr ibat2u, r14
	mtspr ibat2l, r14
	
	mtspr ibat3u, r14
	mtspr ibat3l, r14
	
	mtspr dbat0u, r14
	mtspr dbat0l, r14
	
	mtspr dbat1u, r14
	mtspr dbat1l, r14
	
	mtspr dbat2u, r14
	mtspr dbat2l, r14
	
	mtspr dbat3u, r14
	mtspr dbat3l, r14
	
	blr
	
memsetb:
	rlwimi r5, r5, 8, 16, 23
	rlwimi r5, r5, 16, 0, 15
	
	addi r14, r3, -4
	
	cmplwi 0, r4, 4
	blt 7f
	
	stwu r5, 4(r14)
	beqlr
	
	andi. r15, r14, 3
	add r4, r15, r4
	subf r14, r15, r14
	srwi r15, r4, 2
	mtctr r15
	
	bdz 6f
	
	1:
		stwu r5, 4(r14)
		bdnz 1b
	
	6:
	
	andi. r4, r4, 3
	
	7:
	
	cmpwi 0, r4, 0
	beqlr
	
	mtctr r4
	addi r6, r6, 3
	
	8:
	
	stbu r5, 1(r14)
	bdnz 8b
	
	blr
 
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
 
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	b memcpy_from_uspace_failover_address
 

Rev 1355	Rev 1374
1	#	1	#
2	# Copyright (C) 2005 Martin Decky	2	# Copyright (C) 2005 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.global userspace_asm	33	.global userspace_asm
34	.global iret	34	.global iret
35	.global iret_syscall	35	.global iret_syscall
-		36	.global invalidate_bat
36	.global memsetb	37	.global memsetb
37	.global memcpy	38	.global memcpy
38	.global memcpy_from_uspace	39	.global memcpy_from_uspace
39	.global memcpy_to_uspace	40	.global memcpy_to_uspace
40	.global memcpy_from_uspace_failover_address	41	.global memcpy_from_uspace_failover_address
41	.global memcpy_to_uspace_failover_address	42	.global memcpy_to_uspace_failover_address
42		43
43	userspace_asm:	44	userspace_asm:
44		45
45	# r3 = uspace_uarg	46	# r3 = uspace_uarg
46	# r4 = stack	47	# r4 = stack
47	# r5 = entry	48	# r5 = entry
48		49
49	# disable interrupts	50	# disable interrupts
50		51
51	mfmsr r31	52	mfmsr r31
52	rlwinm r31, r31, 0, 17, 15	53	rlwinm r31, r31, 0, 17, 15
53	mtmsr r31	54	mtmsr r31
54		55
55	# set entry point	56	# set entry point
56		57
57	mtsrr0 r5	58	mtsrr0 r5
58		59
59	# set problem state, enable interrupts	60	# set problem state, enable interrupts
60		61
61	ori r31, r31, msr_pr	62	ori r31, r31, msr_pr
62	ori r31, r31, msr_ee	63	ori r31, r31, msr_ee
63	mtsrr1 r31	64	mtsrr1 r31
64		65
65	# set stack	66	# set stack
66		67
67	mr sp, r4	68	mr sp, r4
68		69
69	# jump to userspace	70	# jump to userspace
70		71
71	rfi	72	rfi
72		73
73	iret:	74	iret:
74		75
75	# disable interrupts	76	# disable interrupts
76		77
77	mfmsr r31	78	mfmsr r31
78	rlwinm r31, r31, 0, 17, 15	79	rlwinm r31, r31, 0, 17, 15
79	mtmsr r31	80	mtmsr r31
80		81
81	lwz r0, 8(sp)	82	lwz r0, 8(sp)
82	lwz r2, 12(sp)	83	lwz r2, 12(sp)
83	lwz r3, 16(sp)	84	lwz r3, 16(sp)
84	lwz r4, 20(sp)	85	lwz r4, 20(sp)
85	lwz r5, 24(sp)	86	lwz r5, 24(sp)
86	lwz r6, 28(sp)	87	lwz r6, 28(sp)
87	lwz r7, 32(sp)	88	lwz r7, 32(sp)
88	lwz r8, 36(sp)	89	lwz r8, 36(sp)
89	lwz r9, 40(sp)	90	lwz r9, 40(sp)
90	lwz r10, 44(sp)	91	lwz r10, 44(sp)
91	lwz r11, 48(sp)	92	lwz r11, 48(sp)
92	lwz r13, 52(sp)	93	lwz r13, 52(sp)
93	lwz r14, 56(sp)	94	lwz r14, 56(sp)
94	lwz r15, 60(sp)	95	lwz r15, 60(sp)
95	lwz r16, 64(sp)	96	lwz r16, 64(sp)
96	lwz r17, 68(sp)	97	lwz r17, 68(sp)
97	lwz r18, 72(sp)	98	lwz r18, 72(sp)
98	lwz r19, 76(sp)	99	lwz r19, 76(sp)
99	lwz r20, 80(sp)	100	lwz r20, 80(sp)
100	lwz r21, 84(sp)	101	lwz r21, 84(sp)
101	lwz r22, 88(sp)	102	lwz r22, 88(sp)
102	lwz r23, 92(sp)	103	lwz r23, 92(sp)
103	lwz r24, 96(sp)	104	lwz r24, 96(sp)
104	lwz r25, 100(sp)	105	lwz r25, 100(sp)
105	lwz r26, 104(sp)	106	lwz r26, 104(sp)
106	lwz r27, 108(sp)	107	lwz r27, 108(sp)
107	lwz r28, 112(sp)	108	lwz r28, 112(sp)
108	lwz r29, 116(sp)	109	lwz r29, 116(sp)
109	lwz r30, 120(sp)	110	lwz r30, 120(sp)
110	lwz r31, 124(sp)	111	lwz r31, 124(sp)
111		112
112	lwz r12, 128(sp)	113	lwz r12, 128(sp)
113	mtcr r12	114	mtcr r12
114		115
115	lwz r12, 132(sp)	116	lwz r12, 132(sp)
116	mtsrr0 r12	117	mtsrr0 r12
117		118
118	lwz r12, 136(sp)	119	lwz r12, 136(sp)
119	mtsrr1 r12	120	mtsrr1 r12
120		121
121	lwz r12, 140(sp)	122	lwz r12, 140(sp)
122	mtlr r12	123	mtlr r12
123		124
124	lwz r12, 144(sp)	125	lwz r12, 144(sp)
125	mtctr r12	126	mtctr r12
126		127
127	lwz r12, 148(sp)	128	lwz r12, 148(sp)
128	mtxer r12	129	mtxer r12
129		130
130	lwz r12, 152(sp)	131	lwz r12, 152(sp)
131	lwz sp, 156(sp)	132	lwz sp, 156(sp)
132		133
133	rfi	134	rfi
134		135
135	iret_syscall:	136	iret_syscall:
136		137
137	# disable interrupts	138	# disable interrupts
138		139
139	mfmsr r31	140	mfmsr r31
140	rlwinm r31, r31, 0, 17, 15	141	rlwinm r31, r31, 0, 17, 15
141	mtmsr r31	142	mtmsr r31
142		143
143	lwz r0, 8(sp)	144	lwz r0, 8(sp)
144	lwz r2, 12(sp)	145	lwz r2, 12(sp)
145	lwz r4, 20(sp)	146	lwz r4, 20(sp)
146	lwz r5, 24(sp)	147	lwz r5, 24(sp)
147	lwz r6, 28(sp)	148	lwz r6, 28(sp)
148	lwz r7, 32(sp)	149	lwz r7, 32(sp)
149	lwz r8, 36(sp)	150	lwz r8, 36(sp)
150	lwz r9, 40(sp)	151	lwz r9, 40(sp)
151	lwz r10, 44(sp)	152	lwz r10, 44(sp)
152	lwz r11, 48(sp)	153	lwz r11, 48(sp)
153	lwz r13, 52(sp)	154	lwz r13, 52(sp)
154	lwz r14, 56(sp)	155	lwz r14, 56(sp)
155	lwz r15, 60(sp)	156	lwz r15, 60(sp)
156	lwz r16, 64(sp)	157	lwz r16, 64(sp)
157	lwz r17, 68(sp)	158	lwz r17, 68(sp)
158	lwz r18, 72(sp)	159	lwz r18, 72(sp)
159	lwz r19, 76(sp)	160	lwz r19, 76(sp)
160	lwz r20, 80(sp)	161	lwz r20, 80(sp)
161	lwz r21, 84(sp)	162	lwz r21, 84(sp)
162	lwz r22, 88(sp)	163	lwz r22, 88(sp)
163	lwz r23, 92(sp)	164	lwz r23, 92(sp)
164	lwz r24, 96(sp)	165	lwz r24, 96(sp)
165	lwz r25, 100(sp)	166	lwz r25, 100(sp)
166	lwz r26, 104(sp)	167	lwz r26, 104(sp)
167	lwz r27, 108(sp)	168	lwz r27, 108(sp)
168	lwz r28, 112(sp)	169	lwz r28, 112(sp)
169	lwz r29, 116(sp)	170	lwz r29, 116(sp)
170	lwz r30, 120(sp)	171	lwz r30, 120(sp)
171	lwz r31, 124(sp)	172	lwz r31, 124(sp)
172		173
173	lwz r12, 128(sp)	174	lwz r12, 128(sp)
174	mtcr r12	175	mtcr r12
175		176
176	lwz r12, 132(sp)	177	lwz r12, 132(sp)
177	mtsrr0 r12	178	mtsrr0 r12
178		179
179	lwz r12, 136(sp)	180	lwz r12, 136(sp)
180	mtsrr1 r12	181	mtsrr1 r12
181		182
182	lwz r12, 140(sp)	183	lwz r12, 140(sp)
183	mtlr r12	184	mtlr r12
184		185
185	lwz r12, 144(sp)	186	lwz r12, 144(sp)
186	mtctr r12	187	mtctr r12
187		188
188	lwz r12, 148(sp)	189	lwz r12, 148(sp)
189	mtxer r12	190	mtxer r12
190		191
191	lwz r12, 152(sp)	192	lwz r12, 152(sp)
192	lwz sp, 156(sp)	193	lwz sp, 156(sp)
193		194
194	rfi	195	rfi
195		196
-		197	invalidate_bat:
-		198
-		199	# invalidate block address translation registers
-		200
-		201	li r14, 0
-		202
-		203	mtspr ibat0u, r14
-		204	mtspr ibat0l, r14
-		205
-		206	mtspr ibat1u, r14
-		207	mtspr ibat1l, r14
-		208
-		209	mtspr ibat2u, r14
-		210	mtspr ibat2l, r14
-		211
-		212	mtspr ibat3u, r14
-		213	mtspr ibat3l, r14
-		214
-		215	mtspr dbat0u, r14
-		216	mtspr dbat0l, r14
-		217
-		218	mtspr dbat1u, r14
-		219	mtspr dbat1l, r14
-		220
-		221	mtspr dbat2u, r14
-		222	mtspr dbat2l, r14
-		223
-		224	mtspr dbat3u, r14
-		225	mtspr dbat3l, r14
-		226
-		227	blr
-		228
196	memsetb:	229	memsetb:
197	rlwimi r5, r5, 8, 16, 23	230	rlwimi r5, r5, 8, 16, 23
198	rlwimi r5, r5, 16, 0, 15	231	rlwimi r5, r5, 16, 0, 15
199		232
200	addi r14, r3, -4	233	addi r14, r3, -4
201		234
202	cmplwi 0, r4, 4	235	cmplwi 0, r4, 4
203	blt 7f	236	blt 7f
204		237
205	stwu r5, 4(r14)	238	stwu r5, 4(r14)
206	beqlr	239	beqlr
207		240
208	andi. r15, r14, 3	241	andi. r15, r14, 3
209	add r4, r15, r4	242	add r4, r15, r4
210	subf r14, r15, r14	243	subf r14, r15, r14
211	srwi r15, r4, 2	244	srwi r15, r4, 2
212	mtctr r15	245	mtctr r15
213		246
214	bdz 6f	247	bdz 6f
215		248
216	1:	249	1:
217	stwu r5, 4(r14)	250	stwu r5, 4(r14)
218	bdnz 1b	251	bdnz 1b
219		252
220	6:	253	6:
221		254
222	andi. r4, r4, 3	255	andi. r4, r4, 3
223		256
224	7:	257	7:
225		258
226	cmpwi 0, r4, 0	259	cmpwi 0, r4, 0
227	beqlr	260	beqlr
228		261
229	mtctr r4	262	mtctr r4
230	addi r6, r6, 3	263	addi r6, r6, 3
231		264
232	8:	265	8:
233		266
234	stbu r5, 1(r14)	267	stbu r5, 1(r14)
235	bdnz 8b	268	bdnz 8b
236		269
237	blr	270	blr
238		271
239	memcpy:	272	memcpy:
240	memcpy_from_uspace:	273	memcpy_from_uspace:
241	memcpy_to_uspace:	274	memcpy_to_uspace:
242		275
243	srwi. r7, r5, 3	276	srwi. r7, r5, 3
244	addi r6, r3, -4	277	addi r6, r3, -4
245	addi r4, r4, -4	278	addi r4, r4, -4
246	beq 2f	279	beq 2f
247		280
248	andi. r0, r6, 3	281	andi. r0, r6, 3
249	mtctr r7	282	mtctr r7
250	bne 5f	283	bne 5f
251		284
252	1:	285	1:
253		286
254	lwz r7, 4(r4)	287	lwz r7, 4(r4)
255	lwzu r8, 8(r4)	288	lwzu r8, 8(r4)
256	stw r7, 4(r6)	289	stw r7, 4(r6)
257	stwu r8, 8(r6)	290	stwu r8, 8(r6)
258	bdnz 1b	291	bdnz 1b
259		292
260	andi. r5, r5, 7	293	andi. r5, r5, 7
261		294
262	2:	295	2:
263		296
264	cmplwi 0, r5, 4	297	cmplwi 0, r5, 4
265	blt 3f	298	blt 3f
266		299
267	lwzu r0, 4(r4)	300	lwzu r0, 4(r4)
268	addi r5, r5, -4	301	addi r5, r5, -4
269	stwu r0, 4(r6)	302	stwu r0, 4(r6)
270		303
271	3:	304	3:
272		305
273	cmpwi 0, r5, 0	306	cmpwi 0, r5, 0
274	beqlr	307	beqlr
275	mtctr r5	308	mtctr r5
276	addi r4, r4, 3	309	addi r4, r4, 3
277	addi r6, r6, 3	310	addi r6, r6, 3
278		311
279	4:	312	4:
280		313
281	lbzu r0, 1(r4)	314	lbzu r0, 1(r4)
282	stbu r0, 1(r6)	315	stbu r0, 1(r6)
283	bdnz 4b	316	bdnz 4b
284	blr	317	blr
285		318
286	5:	319	5:
287		320
288	subfic r0, r0, 4	321	subfic r0, r0, 4
289	mtctr r0	322	mtctr r0
290		323
291	6:	324	6:
292		325
293	lbz r7, 4(r4)	326	lbz r7, 4(r4)
294	addi r4, r4, 1	327	addi r4, r4, 1
295	stb r7, 4(r6)	328	stb r7, 4(r6)
296	addi r6, r6, 1	329	addi r6, r6, 1
297	bdnz 6b	330	bdnz 6b
298	subf r5, r0, r5	331	subf r5, r0, r5
299	rlwinm. r7, r5, 32-3, 3, 31	332	rlwinm. r7, r5, 32-3, 3, 31
300	beq 2b	333	beq 2b
301	mtctr r7	334	mtctr r7
302	b 1b	335	b 1b
303		336
304	memcpy_from_uspace_failover_address:	337	memcpy_from_uspace_failover_address:
305	memcpy_to_uspace_failover_address:	338	memcpy_to_uspace_failover_address:
306	b memcpy_from_uspace_failover_address	339	b memcpy_from_uspace_failover_address
307		340

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(root)/kernel/trunk/arch/ppc32/src/asm.S – Rev 1355 → 1374