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| 1 | # |
1 | # |
| 2 | # Copyright (C) 2005 Martin Decky |
2 | # Copyright (C) 2005 Martin Decky |
| 3 | # All rights reserved. |
3 | # All rights reserved. |
| 4 | # |
4 | # |
| 5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
| 6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
| 7 | # are met: |
7 | # are met: |
| 8 | # |
8 | # |
| 9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
| 10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
| 11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
| 12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
| 13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
| 14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
| 15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
| 16 | # |
16 | # |
| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | # |
27 | # |
| 28 | 28 | ||
| 29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
| 30 | 30 | ||
| 31 | .text |
31 | .text |
| 32 | 32 | ||
| 33 | .global userspace_asm |
33 | .global userspace_asm |
| 34 | .global iret |
34 | .global iret |
| 35 | .global iret_syscall |
35 | .global iret_syscall |
| 36 | .global memsetb |
36 | .global memsetb |
| 37 | .global memcpy |
37 | .global memcpy |
| - | 38 | .global memcpy_from_uspace |
|
| - | 39 | .global memcpy_to_uspace |
|
| - | 40 | .global memcpy_from_uspace_failover_address |
|
| - | 41 | .global memcpy_to_uspace_failover_address |
|
| 38 | 42 | ||
| 39 | userspace_asm: |
43 | userspace_asm: |
| 40 | 44 | ||
| 41 | # r3 = uspace_uarg |
45 | # r3 = uspace_uarg |
| 42 | # r4 = stack |
46 | # r4 = stack |
| 43 | # r5 = entry |
47 | # r5 = entry |
| 44 | 48 | ||
| 45 | # disable interrupts |
49 | # disable interrupts |
| 46 | 50 | ||
| 47 | mfmsr r31 |
51 | mfmsr r31 |
| 48 | rlwinm r31, r31, 0, 17, 15 |
52 | rlwinm r31, r31, 0, 17, 15 |
| 49 | mtmsr r31 |
53 | mtmsr r31 |
| 50 | 54 | ||
| 51 | # set entry point |
55 | # set entry point |
| 52 | 56 | ||
| 53 | mtsrr0 r5 |
57 | mtsrr0 r5 |
| 54 | 58 | ||
| 55 | # set problem state, enable interrupts |
59 | # set problem state, enable interrupts |
| 56 | 60 | ||
| 57 | ori r31, r31, msr_pr |
61 | ori r31, r31, msr_pr |
| 58 | ori r31, r31, msr_ee |
62 | ori r31, r31, msr_ee |
| 59 | mtsrr1 r31 |
63 | mtsrr1 r31 |
| 60 | 64 | ||
| 61 | # set stack |
65 | # set stack |
| 62 | 66 | ||
| 63 | mr sp, r4 |
67 | mr sp, r4 |
| 64 | 68 | ||
| 65 | # jump to userspace |
69 | # jump to userspace |
| 66 | 70 | ||
| 67 | rfi |
71 | rfi |
| 68 | 72 | ||
| 69 | iret: |
73 | iret: |
| 70 | 74 | ||
| 71 | # disable interrupts |
75 | # disable interrupts |
| 72 | 76 | ||
| 73 | mfmsr r31 |
77 | mfmsr r31 |
| 74 | rlwinm r31, r31, 0, 17, 15 |
78 | rlwinm r31, r31, 0, 17, 15 |
| 75 | mtmsr r31 |
79 | mtmsr r31 |
| 76 | 80 | ||
| 77 | lwz r0, 0(sp) |
81 | lwz r0, 0(sp) |
| 78 | lwz r2, 4(sp) |
82 | lwz r2, 4(sp) |
| 79 | lwz r3, 8(sp) |
83 | lwz r3, 8(sp) |
| 80 | lwz r4, 12(sp) |
84 | lwz r4, 12(sp) |
| 81 | lwz r5, 16(sp) |
85 | lwz r5, 16(sp) |
| 82 | lwz r6, 20(sp) |
86 | lwz r6, 20(sp) |
| 83 | lwz r7, 24(sp) |
87 | lwz r7, 24(sp) |
| 84 | lwz r8, 28(sp) |
88 | lwz r8, 28(sp) |
| 85 | lwz r9, 32(sp) |
89 | lwz r9, 32(sp) |
| 86 | lwz r10, 36(sp) |
90 | lwz r10, 36(sp) |
| 87 | lwz r11, 40(sp) |
91 | lwz r11, 40(sp) |
| 88 | lwz r13, 44(sp) |
92 | lwz r13, 44(sp) |
| 89 | lwz r14, 48(sp) |
93 | lwz r14, 48(sp) |
| 90 | lwz r15, 52(sp) |
94 | lwz r15, 52(sp) |
| 91 | lwz r16, 56(sp) |
95 | lwz r16, 56(sp) |
| 92 | lwz r17, 60(sp) |
96 | lwz r17, 60(sp) |
| 93 | lwz r18, 64(sp) |
97 | lwz r18, 64(sp) |
| 94 | lwz r19, 68(sp) |
98 | lwz r19, 68(sp) |
| 95 | lwz r20, 72(sp) |
99 | lwz r20, 72(sp) |
| 96 | lwz r21, 76(sp) |
100 | lwz r21, 76(sp) |
| 97 | lwz r22, 80(sp) |
101 | lwz r22, 80(sp) |
| 98 | lwz r23, 84(sp) |
102 | lwz r23, 84(sp) |
| 99 | lwz r24, 88(sp) |
103 | lwz r24, 88(sp) |
| 100 | lwz r25, 92(sp) |
104 | lwz r25, 92(sp) |
| 101 | lwz r26, 96(sp) |
105 | lwz r26, 96(sp) |
| 102 | lwz r27, 100(sp) |
106 | lwz r27, 100(sp) |
| 103 | lwz r28, 104(sp) |
107 | lwz r28, 104(sp) |
| 104 | lwz r29, 108(sp) |
108 | lwz r29, 108(sp) |
| 105 | lwz r30, 112(sp) |
109 | lwz r30, 112(sp) |
| 106 | lwz r31, 116(sp) |
110 | lwz r31, 116(sp) |
| 107 | 111 | ||
| 108 | lwz r12, 120(sp) |
112 | lwz r12, 120(sp) |
| 109 | mtcr r12 |
113 | mtcr r12 |
| 110 | 114 | ||
| 111 | lwz r12, 124(sp) |
115 | lwz r12, 124(sp) |
| 112 | mtsrr0 r12 |
116 | mtsrr0 r12 |
| 113 | 117 | ||
| 114 | lwz r12, 128(sp) |
118 | lwz r12, 128(sp) |
| 115 | mtsrr1 r12 |
119 | mtsrr1 r12 |
| 116 | 120 | ||
| 117 | lwz r12, 132(sp) |
121 | lwz r12, 132(sp) |
| 118 | mtlr r12 |
122 | mtlr r12 |
| 119 | 123 | ||
| 120 | lwz r12, 136(sp) |
124 | lwz r12, 136(sp) |
| 121 | mtctr r12 |
125 | mtctr r12 |
| 122 | 126 | ||
| 123 | lwz r12, 140(sp) |
127 | lwz r12, 140(sp) |
| 124 | mtxer r12 |
128 | mtxer r12 |
| 125 | 129 | ||
| 126 | lwz r12, 144(sp) |
130 | lwz r12, 144(sp) |
| 127 | lwz sp, 148(sp) |
131 | lwz sp, 148(sp) |
| 128 | 132 | ||
| 129 | rfi |
133 | rfi |
| 130 | 134 | ||
| 131 | iret_syscall: |
135 | iret_syscall: |
| 132 | 136 | ||
| 133 | # disable interrupts |
137 | # disable interrupts |
| 134 | 138 | ||
| 135 | mfmsr r31 |
139 | mfmsr r31 |
| 136 | rlwinm r31, r31, 0, 17, 15 |
140 | rlwinm r31, r31, 0, 17, 15 |
| 137 | mtmsr r31 |
141 | mtmsr r31 |
| 138 | 142 | ||
| 139 | lwz r0, 0(sp) |
143 | lwz r0, 0(sp) |
| 140 | lwz r2, 4(sp) |
144 | lwz r2, 4(sp) |
| 141 | lwz r4, 12(sp) |
145 | lwz r4, 12(sp) |
| 142 | lwz r5, 16(sp) |
146 | lwz r5, 16(sp) |
| 143 | lwz r6, 20(sp) |
147 | lwz r6, 20(sp) |
| 144 | lwz r7, 24(sp) |
148 | lwz r7, 24(sp) |
| 145 | lwz r8, 28(sp) |
149 | lwz r8, 28(sp) |
| 146 | lwz r9, 32(sp) |
150 | lwz r9, 32(sp) |
| 147 | lwz r10, 36(sp) |
151 | lwz r10, 36(sp) |
| 148 | lwz r11, 40(sp) |
152 | lwz r11, 40(sp) |
| 149 | lwz r13, 44(sp) |
153 | lwz r13, 44(sp) |
| 150 | lwz r14, 48(sp) |
154 | lwz r14, 48(sp) |
| 151 | lwz r15, 52(sp) |
155 | lwz r15, 52(sp) |
| 152 | lwz r16, 56(sp) |
156 | lwz r16, 56(sp) |
| 153 | lwz r17, 60(sp) |
157 | lwz r17, 60(sp) |
| 154 | lwz r18, 64(sp) |
158 | lwz r18, 64(sp) |
| 155 | lwz r19, 68(sp) |
159 | lwz r19, 68(sp) |
| 156 | lwz r20, 72(sp) |
160 | lwz r20, 72(sp) |
| 157 | lwz r21, 76(sp) |
161 | lwz r21, 76(sp) |
| 158 | lwz r22, 80(sp) |
162 | lwz r22, 80(sp) |
| 159 | lwz r23, 84(sp) |
163 | lwz r23, 84(sp) |
| 160 | lwz r24, 88(sp) |
164 | lwz r24, 88(sp) |
| 161 | lwz r25, 92(sp) |
165 | lwz r25, 92(sp) |
| 162 | lwz r26, 96(sp) |
166 | lwz r26, 96(sp) |
| 163 | lwz r27, 100(sp) |
167 | lwz r27, 100(sp) |
| 164 | lwz r28, 104(sp) |
168 | lwz r28, 104(sp) |
| 165 | lwz r29, 108(sp) |
169 | lwz r29, 108(sp) |
| 166 | lwz r30, 112(sp) |
170 | lwz r30, 112(sp) |
| 167 | lwz r31, 116(sp) |
171 | lwz r31, 116(sp) |
| 168 | 172 | ||
| 169 | lwz r12, 120(sp) |
173 | lwz r12, 120(sp) |
| 170 | mtcr r12 |
174 | mtcr r12 |
| 171 | 175 | ||
| 172 | lwz r12, 124(sp) |
176 | lwz r12, 124(sp) |
| 173 | mtsrr0 r12 |
177 | mtsrr0 r12 |
| 174 | 178 | ||
| 175 | lwz r12, 128(sp) |
179 | lwz r12, 128(sp) |
| 176 | mtsrr1 r12 |
180 | mtsrr1 r12 |
| 177 | 181 | ||
| 178 | lwz r12, 132(sp) |
182 | lwz r12, 132(sp) |
| 179 | mtlr r12 |
183 | mtlr r12 |
| 180 | 184 | ||
| 181 | lwz r12, 136(sp) |
185 | lwz r12, 136(sp) |
| 182 | mtctr r12 |
186 | mtctr r12 |
| 183 | 187 | ||
| 184 | lwz r12, 140(sp) |
188 | lwz r12, 140(sp) |
| 185 | mtxer r12 |
189 | mtxer r12 |
| 186 | 190 | ||
| 187 | lwz r12, 144(sp) |
191 | lwz r12, 144(sp) |
| 188 | lwz sp, 148(sp) |
192 | lwz sp, 148(sp) |
| 189 | 193 | ||
| 190 | rfi |
194 | rfi |
| 191 | 195 | ||
| 192 | memsetb: |
196 | memsetb: |
| 193 | rlwimi r5, r5, 8, 16, 23 |
197 | rlwimi r5, r5, 8, 16, 23 |
| 194 | rlwimi r5, r5, 16, 0, 15 |
198 | rlwimi r5, r5, 16, 0, 15 |
| 195 | 199 | ||
| 196 | addi r14, r3, -4 |
200 | addi r14, r3, -4 |
| 197 | 201 | ||
| 198 | cmplwi 0, r4, 4 |
202 | cmplwi 0, r4, 4 |
| 199 | blt 7f |
203 | blt 7f |
| 200 | 204 | ||
| 201 | stwu r5, 4(r14) |
205 | stwu r5, 4(r14) |
| 202 | beqlr |
206 | beqlr |
| 203 | 207 | ||
| 204 | andi. r15, r14, 3 |
208 | andi. r15, r14, 3 |
| 205 | add r4, r15, r4 |
209 | add r4, r15, r4 |
| 206 | subf r14, r15, r14 |
210 | subf r14, r15, r14 |
| 207 | srwi r15, r4, 2 |
211 | srwi r15, r4, 2 |
| 208 | mtctr r15 |
212 | mtctr r15 |
| 209 | 213 | ||
| 210 | bdz 6f |
214 | bdz 6f |
| 211 | 215 | ||
| 212 | 1: |
216 | 1: |
| 213 | stwu r5, 4(r14) |
217 | stwu r5, 4(r14) |
| 214 | bdnz 1b |
218 | bdnz 1b |
| 215 | 219 | ||
| 216 | 6: |
220 | 6: |
| 217 | 221 | ||
| 218 | andi. r4, r4, 3 |
222 | andi. r4, r4, 3 |
| 219 | 223 | ||
| 220 | 7: |
224 | 7: |
| 221 | 225 | ||
| 222 | cmpwi 0, r4, 0 |
226 | cmpwi 0, r4, 0 |
| 223 | beqlr |
227 | beqlr |
| 224 | 228 | ||
| 225 | mtctr r4 |
229 | mtctr r4 |
| 226 | addi r6, r6, 3 |
230 | addi r6, r6, 3 |
| 227 | 231 | ||
| 228 | 8: |
232 | 8: |
| 229 | 233 | ||
| 230 | stbu r5, 1(r14) |
234 | stbu r5, 1(r14) |
| 231 | bdnz 8b |
235 | bdnz 8b |
| 232 | 236 | ||
| 233 | blr |
237 | blr |
| 234 | 238 | ||
| 235 | memcpy: |
239 | memcpy: |
| - | 240 | memcpy_from_uspace: |
|
| - | 241 | memcpy_to_uspace: |
|
| - | 242 | ||
| 236 | srwi. r7, r5, 3 |
243 | srwi. r7, r5, 3 |
| 237 | addi r6, r3, -4 |
244 | addi r6, r3, -4 |
| 238 | addi r4, r4, -4 |
245 | addi r4, r4, -4 |
| 239 | beq 2f |
246 | beq 2f |
| 240 | 247 | ||
| 241 | andi. r0, r6, 3 |
248 | andi. r0, r6, 3 |
| 242 | mtctr r7 |
249 | mtctr r7 |
| 243 | bne 5f |
250 | bne 5f |
| 244 | 251 | ||
| 245 | 1: |
252 | 1: |
| 246 | 253 | ||
| 247 | lwz r7, 4(r4) |
254 | lwz r7, 4(r4) |
| 248 | lwzu r8, 8(r4) |
255 | lwzu r8, 8(r4) |
| 249 | stw r7, 4(r6) |
256 | stw r7, 4(r6) |
| 250 | stwu r8, 8(r6) |
257 | stwu r8, 8(r6) |
| 251 | bdnz 1b |
258 | bdnz 1b |
| 252 | 259 | ||
| 253 | andi. r5, r5, 7 |
260 | andi. r5, r5, 7 |
| 254 | 261 | ||
| 255 | 2: |
262 | 2: |
| 256 | 263 | ||
| 257 | cmplwi 0, r5, 4 |
264 | cmplwi 0, r5, 4 |
| 258 | blt 3f |
265 | blt 3f |
| 259 | 266 | ||
| 260 | lwzu r0, 4(r4) |
267 | lwzu r0, 4(r4) |
| 261 | addi r5, r5, -4 |
268 | addi r5, r5, -4 |
| 262 | stwu r0, 4(r6) |
269 | stwu r0, 4(r6) |
| 263 | 270 | ||
| 264 | 3: |
271 | 3: |
| 265 | 272 | ||
| 266 | cmpwi 0, r5, 0 |
273 | cmpwi 0, r5, 0 |
| 267 | beqlr |
274 | beqlr |
| 268 | mtctr r5 |
275 | mtctr r5 |
| 269 | addi r4, r4, 3 |
276 | addi r4, r4, 3 |
| 270 | addi r6, r6, 3 |
277 | addi r6, r6, 3 |
| 271 | 278 | ||
| 272 | 4: |
279 | 4: |
| 273 | 280 | ||
| 274 | lbzu r0, 1(r4) |
281 | lbzu r0, 1(r4) |
| 275 | stbu r0, 1(r6) |
282 | stbu r0, 1(r6) |
| 276 | bdnz 4b |
283 | bdnz 4b |
| 277 | blr |
284 | blr |
| 278 | 285 | ||
| 279 | 5: |
286 | 5: |
| 280 | 287 | ||
| 281 | subfic r0, r0, 4 |
288 | subfic r0, r0, 4 |
| 282 | mtctr r0 |
289 | mtctr r0 |
| 283 | 290 | ||
| 284 | 6: |
291 | 6: |
| 285 | 292 | ||
| 286 | lbz r7, 4(r4) |
293 | lbz r7, 4(r4) |
| 287 | addi r4, r4, 1 |
294 | addi r4, r4, 1 |
| 288 | stb r7, 4(r6) |
295 | stb r7, 4(r6) |
| 289 | addi r6, r6, 1 |
296 | addi r6, r6, 1 |
| 290 | bdnz 6b |
297 | bdnz 6b |
| 291 | subf r5, r0, r5 |
298 | subf r5, r0, r5 |
| 292 | rlwinm. r7, r5, 32-3, 3, 31 |
299 | rlwinm. r7, r5, 32-3, 3, 31 |
| 293 | beq 2b |
300 | beq 2b |
| 294 | mtctr r7 |
301 | mtctr r7 |
| 295 | b 1b |
302 | b 1b |
| - | 303 | ||
| - | 304 | memcpy_from_uspace_failover_address: |
|
| - | 305 | memcpy_to_uspace_failover_address: |
|
| - | 306 | b memcpy_from_uspace_failover_address |
|
| 296 | 307 | ||