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| Rev 1220 | Rev 1267 | ||
|---|---|---|---|
| Line 37... | Line 37... | ||
| 37 | 37 | ||
| 38 | userspace_asm: |
38 | userspace_asm: |
| 39 | 39 | ||
| 40 | # r3 = uspace_uarg |
40 | # r3 = uspace_uarg |
| 41 | # r4 = stack |
41 | # r4 = stack |
| 42 | # r5 = entry |
42 | # r5 = entry |
| - | 43 | ||
| - | 44 | # disable interrupts |
|
| 43 | 45 | ||
| 44 | mfmsr r31 |
46 | mfmsr r31 |
| 45 | rlwinm r31, r31, 0, 17, 15 |
47 | rlwinm r31, r31, 0, 17, 15 |
| 46 | mtmsr r31 |
48 | mtmsr r31 |
| 47 | 49 | ||
| Line 49... | Line 51... | ||
| 49 | 51 | ||
| 50 | mtsrr0 r5 |
52 | mtsrr0 r5 |
| 51 | 53 | ||
| 52 | # set problem state, enable interrupts |
54 | # set problem state, enable interrupts |
| 53 | 55 | ||
| 54 | ori r31, r31, 1 << 14 |
56 | ori r31, r31, msr_pr |
| 55 | ori r31, r31, 1 << 15 |
57 | ori r31, r31, msr_ee |
| 56 | mtsrr1 r31 |
58 | mtsrr1 r31 |
| 57 | 59 | ||
| 58 | # set stack |
60 | # set stack |
| 59 | 61 | ||
| 60 | mr sp, r4 |
62 | mr sp, r4 |
| Line 62... | Line 64... | ||
| 62 | # jump to userspace |
64 | # jump to userspace |
| 63 | 65 | ||
| 64 | rfi |
66 | rfi |
| 65 | 67 | ||
| 66 | iret: |
68 | iret: |
| 67 | lwz r3, 144(sp) |
- | |
| 68 | mtxer r3 |
- | |
| 69 | - | ||
| 70 | lwz r3, 140(sp) |
- | |
| 71 | mtctr r3 |
- | |
| 72 | - | ||
| 73 | lwz r3, 136(sp) |
- | |
| 74 | mtcr r3 |
- | |
| 75 | - | ||
| 76 | lwz r3, 132(sp) |
- | |
| 77 | mtlr r3 |
- | |
| 78 | - | ||
| 79 | lwz r3, 128(sp) |
- | |
| 80 | mtspr srr1, r3 |
- | |
| 81 | - | ||
| 82 | lwz r3, 124(sp) |
- | |
| 83 | mtspr srr0, r3 |
- | |
| 84 | - | ||
| 85 | lwz r0, 0(sp) |
69 | lwz r0, 0(sp) |
| 86 | lwz r2, 4(sp) |
70 | lwz r2, 4(sp) |
| 87 | lwz r3, 8(sp) |
71 | lwz r3, 8(sp) |
| 88 | lwz r4, 12(sp) |
72 | lwz r4, 12(sp) |
| 89 | lwz r5, 16(sp) |
73 | lwz r5, 16(sp) |
| Line 91... | Line 75... | ||
| 91 | lwz r7, 24(sp) |
75 | lwz r7, 24(sp) |
| 92 | lwz r8, 28(sp) |
76 | lwz r8, 28(sp) |
| 93 | lwz r9, 32(sp) |
77 | lwz r9, 32(sp) |
| 94 | lwz r10, 36(sp) |
78 | lwz r10, 36(sp) |
| 95 | lwz r11, 40(sp) |
79 | lwz r11, 40(sp) |
| 96 | lwz r12, 44(sp) |
80 | lwz r13, 44(sp) |
| 97 | lwz r13, 48(sp) |
81 | lwz r14, 48(sp) |
| 98 | lwz r14, 52(sp) |
82 | lwz r15, 52(sp) |
| 99 | lwz r15, 56(sp) |
83 | lwz r16, 56(sp) |
| 100 | lwz r16, 60(sp) |
84 | lwz r17, 60(sp) |
| 101 | lwz r17, 64(sp) |
85 | lwz r18, 64(sp) |
| 102 | lwz r18, 68(sp) |
86 | lwz r19, 68(sp) |
| 103 | lwz r19, 72(sp) |
87 | lwz r20, 72(sp) |
| 104 | lwz r20, 76(sp) |
88 | lwz r21, 76(sp) |
| 105 | lwz r21, 80(sp) |
89 | lwz r22, 80(sp) |
| 106 | lwz r22, 84(sp) |
90 | lwz r23, 84(sp) |
| 107 | lwz r23, 88(sp) |
91 | lwz r24, 88(sp) |
| 108 | lwz r24, 92(sp) |
92 | lwz r25, 92(sp) |
| 109 | lwz r25, 96(sp) |
93 | lwz r26, 96(sp) |
| 110 | lwz r26, 100(sp) |
94 | lwz r27, 100(sp) |
| 111 | lwz r27, 104(sp) |
95 | lwz r28, 104(sp) |
| 112 | lwz r28, 108(sp) |
96 | lwz r29, 108(sp) |
| 113 | lwz r29, 112(sp) |
97 | lwz r30, 112(sp) |
| 114 | lwz r30, 116(sp) |
98 | lwz r31, 116(sp) |
| - | 99 | ||
| 115 | lwz r31, 120(sp) |
100 | lwz r12, 120(sp) |
| - | 101 | mtsrr0 r12 |
|
| - | 102 | ||
| - | 103 | lwz r12, 124(sp) |
|
| - | 104 | mtsrr1 r12 |
|
| - | 105 | ||
| - | 106 | lwz r12, 128(sp) |
|
| - | 107 | mtlr r12 |
|
| - | 108 | ||
| - | 109 | lwz r12, 132(sp) |
|
| - | 110 | mtcr r12 |
|
| 116 | 111 | ||
| - | 112 | lwz r12, 136(sp) |
|
| - | 113 | mtctr r12 |
|
| - | 114 | ||
| - | 115 | lwz r12, 140(sp) |
|
| - | 116 | mtxer r12 |
|
| - | 117 | ||
| 117 | mfspr sp, sprg1 |
118 | mfsprg1 sp |
| - | 119 | mfsprg2 r12 |
|
| 118 | 120 | ||
| 119 | rfi |
121 | rfi |
| 120 | 122 | ||
| 121 | memsetb: |
123 | memsetb: |
| 122 | rlwimi r5, r5, 8, 16, 23 |
124 | rlwimi r5, r5, 8, 16, 23 |