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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __ppc32_MACRO_H__ |
29 | #ifndef __ppc32_REGNAME_H__ |
| 30 | #define __ppc32_MACRO_H__ |
30 | #define __ppc32_REGNAME_H__ |
| 31 | - | ||
| 32 | /* |
- | |
| 33 | * PPC assembler macros |
- | |
| 34 | */ |
- | |
| 35 | 31 | ||
| 36 | /* Condition Register Bit Fields */ |
32 | /* Condition Register Bit Fields */ |
| 37 | #define cr0 0 |
33 | #define cr0 0 |
| 38 | #define cr1 1 |
34 | #define cr1 1 |
| 39 | #define cr2 2 |
35 | #define cr2 2 |
| Line 191... | Line 187... | ||
| 191 | #define sprg1 273 |
187 | #define sprg1 273 |
| 192 | #define sprg2 274 |
188 | #define sprg2 274 |
| 193 | #define sprg3 275 |
189 | #define sprg3 275 |
| 194 | #define prv 287 |
190 | #define prv 287 |
| 195 | 191 | ||
| 196 | .macro REGISTERS_STORE r |
- | |
| 197 | stw r0, 0(\r) |
- | |
| 198 | stw r1, 4(\r) |
- | |
| 199 | stw r2, 8(\r) |
- | |
| 200 | stw r3, 12(\r) |
- | |
| 201 | stw r4, 16(\r) |
- | |
| 202 | stw r5, 20(\r) |
- | |
| 203 | stw r6, 24(\r) |
- | |
| 204 | stw r7, 28(\r) |
- | |
| 205 | stw r8, 32(\r) |
- | |
| 206 | stw r9, 36(\r) |
- | |
| 207 | stw r10, 40(\r) |
- | |
| 208 | stw r11, 44(\r) |
- | |
| 209 | stw r12, 48(\r) |
- | |
| 210 | stw r13, 52(\r) |
- | |
| 211 | stw r14, 56(\r) |
- | |
| 212 | stw r15, 60(\r) |
- | |
| 213 | stw r16, 64(\r) |
- | |
| 214 | stw r17, 68(\r) |
- | |
| 215 | stw r18, 72(\r) |
- | |
| 216 | stw r19, 76(\r) |
- | |
| 217 | stw r20, 80(\r) |
- | |
| 218 | stw r21, 84(\r) |
- | |
| 219 | stw r22, 88(\r) |
- | |
| 220 | stw r23, 92(\r) |
- | |
| 221 | stw r24, 96(\r) |
- | |
| 222 | stw r25, 100(\r) |
- | |
| 223 | stw r26, 104(\r) |
- | |
| 224 | stw r27, 108(\r) |
- | |
| 225 | stw r28, 112(\r) |
- | |
| 226 | stw r29, 116(\r) |
- | |
| 227 | stw r30, 120(\r) |
- | |
| 228 | stw r31, 124(\r) |
- | |
| 229 | .endm |
- | |
| 230 | - | ||
| 231 | .macro REGISTERS_LOAD r |
- | |
| 232 | lwz r0, 0(\r) |
- | |
| 233 | lwz r1, 4(\r) |
- | |
| 234 | lwz r2, 8(\r) |
- | |
| 235 | lwz r3, 12(\r) |
- | |
| 236 | lwz r4, 16(\r) |
- | |
| 237 | lwz r5, 20(\r) |
- | |
| 238 | lwz r6, 24(\r) |
- | |
| 239 | lwz r7, 28(\r) |
- | |
| 240 | lwz r8, 32(\r) |
- | |
| 241 | lwz r9, 36(\r) |
- | |
| 242 | lwz r10, 40(\r) |
- | |
| 243 | lwz r11, 44(\r) |
- | |
| 244 | lwz r12, 48(\r) |
- | |
| 245 | lwz r13, 52(\r) |
- | |
| 246 | lwz r14, 56(\r) |
- | |
| 247 | lwz r15, 60(\r) |
- | |
| 248 | lwz r16, 64(\r) |
- | |
| 249 | lwz r17, 68(\r) |
- | |
| 250 | lwz r18, 72(\r) |
- | |
| 251 | lwz r19, 76(\r) |
- | |
| 252 | lwz r20, 80(\r) |
- | |
| 253 | lwz r21, 84(\r) |
- | |
| 254 | lwz r22, 88(\r) |
- | |
| 255 | lwz r23, 92(\r) |
- | |
| 256 | lwz r24, 96(\r) |
- | |
| 257 | lwz r25, 100(\r) |
- | |
| 258 | lwz r26, 104(\r) |
- | |
| 259 | lwz r27, 108(\r) |
- | |
| 260 | lwz r28, 112(\r) |
- | |
| 261 | lwz r29, 116(\r) |
- | |
| 262 | lwz r30, 120(\r) |
- | |
| 263 | lwz r31, 124(\r) |
- | |
| 264 | .endm |
- | |
| 265 | - | ||
| 266 | #endif |
192 | #endif |