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#
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#
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# Copyright (C) 2003-2004 Jakub Jermar
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# Copyright (C) 2003-2004 Jakub Jermar
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# All rights reserved.
3
# All rights reserved.
4
#
4
#
5
# Redistribution and use in source and binary forms, with or without
5
# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
6
# modification, are permitted provided that the following conditions
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# are met:
7
# are met:
8
#
8
#
9
# - Redistributions of source code must retain the above copyright
9
# - Redistributions of source code must retain the above copyright
10
#   notice, this list of conditions and the following disclaimer.
10
#   notice, this list of conditions and the following disclaimer.
11
# - Redistributions in binary form must reproduce the above copyright
11
# - Redistributions in binary form must reproduce the above copyright
12
#   notice, this list of conditions and the following disclaimer in the
12
#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
13
#   documentation and/or other materials provided with the distribution.
14
# - The name of the author may not be used to endorse or promote products
14
# - The name of the author may not be used to endorse or promote products
15
#   derived from this software without specific prior written permission.
15
#   derived from this software without specific prior written permission.
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#
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
27
#
28
 
28
 
29
#include <arch/asm/regname.h>
29
#include <arch/asm/regname.h>
30
#include <arch/mm/page.h>
30
#include <arch/mm/page.h>
31
#include <arch/asm/boot.h>
31
#include <arch/asm/boot.h>
32
#include <arch/context_offset.h>
32
#include <arch/context_offset.h>
33
	
33
	
34
.text
34
.text
35
 
35
 
36
.set noat
36
.set noat
37
.set noreorder
37
.set noreorder
38
.set nomacro
38
.set nomacro
39
 
39
 
40
.global kernel_image_start
40
.global kernel_image_start
41
.global tlb_refill_entry
41
.global tlb_refill_entry
42
.global cache_error_entry
42
.global cache_error_entry
43
.global exception_entry
43
.global exception_entry
44
.global userspace_asm
44
.global userspace_asm
45
 
45
 
-
 
46
# Which status bits should are thread-local
-
 
47
#define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE
-
 
48
	
46
# Save registers to space defined by \r
49
# Save registers to space defined by \r
47
# We will change $at on the way
50
# We will change status: Disable ERL,EXL,UM,IE
-
 
51
# These changes will be automatically reversed in REGISTER_LOAD
48
.macro REGISTERS_STORE r
52
.macro REGISTERS_STORE_AND_EXC_RESET r
49
	sw $at,EOFFSET_AT(\r)
53
	sw $at,EOFFSET_AT(\r)
50
	sw $v0,EOFFSET_V0(\r)
54
	sw $v0,EOFFSET_V0(\r)
51
	sw $v1,EOFFSET_V1(\r)
55
	sw $v1,EOFFSET_V1(\r)
52
	sw $a0,EOFFSET_A0(\r)
56
	sw $a0,EOFFSET_A0(\r)
53
	sw $a1,EOFFSET_A1(\r)
57
	sw $a1,EOFFSET_A1(\r)
54
	sw $a2,EOFFSET_A2(\r)
58
	sw $a2,EOFFSET_A2(\r)
55
	sw $a3,EOFFSET_A3(\r)
59
	sw $a3,EOFFSET_A3(\r)
56
	sw $t0,EOFFSET_T0(\r)
60
	sw $t0,EOFFSET_T0(\r)
57
	sw $t1,EOFFSET_T1(\r)
61
	sw $t1,EOFFSET_T1(\r)
58
	sw $t2,EOFFSET_T2(\r)
62
	sw $t2,EOFFSET_T2(\r)
59
	sw $t3,EOFFSET_T3(\r)
63
	sw $t3,EOFFSET_T3(\r)
60
	sw $t4,EOFFSET_T4(\r)
64
	sw $t4,EOFFSET_T4(\r)
61
	sw $t5,EOFFSET_T5(\r)
65
	sw $t5,EOFFSET_T5(\r)
62
	sw $t6,EOFFSET_T6(\r)
66
	sw $t6,EOFFSET_T6(\r)
63
	sw $t7,EOFFSET_T7(\r)
67
	sw $t7,EOFFSET_T7(\r)
64
	sw $t8,EOFFSET_T8(\r)
68
	sw $t8,EOFFSET_T8(\r)
65
	sw $t9,EOFFSET_T9(\r)
69
	sw $t9,EOFFSET_T9(\r)
66
 
70
 
67
	mflo $at
71
	mflo $at
68
	sw $at, EOFFSET_LO(\r)
72
	sw $at, EOFFSET_LO(\r)
69
	mfhi $at
73
	mfhi $at
70
	sw $at, EOFFSET_HI(\r)
74
	sw $at, EOFFSET_HI(\r)
71
	
75
	
72
#ifdef CONFIG_DEBUG_ALLREGS	
76
#ifdef CONFIG_DEBUG_ALLREGS	
73
	sw $s0,EOFFSET_S0(\r)
77
	sw $s0,EOFFSET_S0(\r)
74
	sw $s1,EOFFSET_S1(\r)
78
	sw $s1,EOFFSET_S1(\r)
75
	sw $s2,EOFFSET_S2(\r)
79
	sw $s2,EOFFSET_S2(\r)
76
	sw $s3,EOFFSET_S3(\r)
80
	sw $s3,EOFFSET_S3(\r)
77
	sw $s4,EOFFSET_S4(\r)
81
	sw $s4,EOFFSET_S4(\r)
78
	sw $s5,EOFFSET_S5(\r)
82
	sw $s5,EOFFSET_S5(\r)
79
	sw $s6,EOFFSET_S6(\r)
83
	sw $s6,EOFFSET_S6(\r)
80
	sw $s7,EOFFSET_S7(\r)
84
	sw $s7,EOFFSET_S7(\r)
81
	sw $s8,EOFFSET_S8(\r)
85
	sw $s8,EOFFSET_S8(\r)
82
#endif
86
#endif
83
	
87
	
84
	sw $gp,EOFFSET_GP(\r)
88
	sw $gp,EOFFSET_GP(\r)
85
	sw $ra,EOFFSET_RA(\r)
89
	sw $ra,EOFFSET_RA(\r)
86
	sw $sp,EOFFSET_SP(\r)
90
	sw $sp,EOFFSET_SP(\r)
87
 
91
 
88
	mfc0 $at, $status
92
	mfc0 $t0, $status
-
 
93
	mfc0 $t1, $epc
-
 
94
	
-
 
95
	and $t2, $t0, REG_SAVE_MASK  # Save only KSU,EXL,ERL,IE
-
 
96
	li $t3, ~(0x1f)
-
 
97
	and $t0, $t0, $t3           # Clear KSU,EXL,ERL,IE
-
 
98
	
89
	sw $at,EOFFSET_STATUS(\r)
99
	sw $t2,EOFFSET_STATUS(\r)
90
	mfc0 $at, $epc
-
 
91
	sw $at,EOFFSET_EPC(\r)
100
	sw $t1,EOFFSET_EPC(\r)
-
 
101
	mtc0 $t0, $status
92
.endm
102
.endm
93
 
103
 
94
.macro REGISTERS_LOAD r
104
.macro REGISTERS_LOAD r
-
 
105
	# Update only UM,EXR,IE from status, the rest
-
 
106
	# is controlled by OS and not bound to task
-
 
107
	mfc0 $t0, $status
-
 
108
	lw $t1,EOFFSET_STATUS(\r)
-
 
109
 
-
 
110
	li $t2, ~REG_SAVE_MASK    # Mask UM,EXL,ERL,IE
-
 
111
	and $t0, $t0, $t2
-
 
112
	
-
 
113
	or $t0, $t0, $t1   # Copy UM,EXL,ERL,IE from saved status
-
 
114
	mtc0 $t0, $status
-
 
115
	
95
	lw $v0,EOFFSET_V0(\r)
116
	lw $v0,EOFFSET_V0(\r)
96
	lw $v1,EOFFSET_V1(\r)
117
	lw $v1,EOFFSET_V1(\r)
97
	lw $a0,EOFFSET_A0(\r)
118
	lw $a0,EOFFSET_A0(\r)
98
	lw $a1,EOFFSET_A1(\r)
119
	lw $a1,EOFFSET_A1(\r)
99
	lw $a2,EOFFSET_A2(\r)
120
	lw $a2,EOFFSET_A2(\r)
100
	lw $a3,EOFFSET_A3(\r)
121
	lw $a3,EOFFSET_A3(\r)
101
	lw $t0,EOFFSET_T0(\r)
122
	lw $t0,EOFFSET_T0(\r)
102
	lw $t1,EOFFSET_T1(\r)
123
	lw $t1,EOFFSET_T1(\r)
103
	lw $t2,EOFFSET_T2(\r)
124
	lw $t2,EOFFSET_T2(\r)
104
	lw $t3,EOFFSET_T3(\r)
125
	lw $t3,EOFFSET_T3(\r)
105
	lw $t4,EOFFSET_T4(\r)
126
	lw $t4,EOFFSET_T4(\r)
106
	lw $t5,EOFFSET_T5(\r)
127
	lw $t5,EOFFSET_T5(\r)
107
	lw $t6,EOFFSET_T6(\r)
128
	lw $t6,EOFFSET_T6(\r)
108
	lw $t7,EOFFSET_T7(\r)
129
	lw $t7,EOFFSET_T7(\r)
109
	lw $t8,EOFFSET_T8(\r)
130
	lw $t8,EOFFSET_T8(\r)
110
	lw $t9,EOFFSET_T9(\r)
131
	lw $t9,EOFFSET_T9(\r)
111
	
132
	
112
#ifdef CONFIG_DEBUG_ALLREGS	
133
#ifdef CONFIG_DEBUG_ALLREGS	
113
	lw $s0,EOFFSET_S0(\r)
134
	lw $s0,EOFFSET_S0(\r)
114
	lw $s1,EOFFSET_S1(\r)
135
	lw $s1,EOFFSET_S1(\r)
115
	lw $s2,EOFFSET_S2(\r)
136
	lw $s2,EOFFSET_S2(\r)
116
	lw $s3,EOFFSET_S3(\r)
137
	lw $s3,EOFFSET_S3(\r)
117
	lw $s4,EOFFSET_S4(\r)
138
	lw $s4,EOFFSET_S4(\r)
118
	lw $s5,EOFFSET_S5(\r)
139
	lw $s5,EOFFSET_S5(\r)
119
	lw $s6,EOFFSET_S6(\r)
140
	lw $s6,EOFFSET_S6(\r)
120
	lw $s7,EOFFSET_S7(\r)
141
	lw $s7,EOFFSET_S7(\r)
121
	lw $s8,EOFFSET_S8(\r)
142
	lw $s8,EOFFSET_S8(\r)
122
#endif
143
#endif
123
	lw $gp,EOFFSET_GP(\r)
144
	lw $gp,EOFFSET_GP(\r)
124
	lw $ra,EOFFSET_RA(\r)
145
	lw $ra,EOFFSET_RA(\r)
125
	
146
	
126
	lw $at,EOFFSET_LO(\r)
147
	lw $at,EOFFSET_LO(\r)
127
	mtlo $at
148
	mtlo $at
128
	lw $at,EOFFSET_HI(\r)
149
	lw $at,EOFFSET_HI(\r)
129
	mthi $at
150
	mthi $at
130
 
151
 
131
	lw $at,EOFFSET_STATUS(\r)
-
 
132
	mtc0 $at, $status
-
 
133
	lw $at,EOFFSET_EPC(\r)
152
	lw $at,EOFFSET_EPC(\r)
134
	mtc0 $at, $epc
153
	mtc0 $at, $epc
135
	
154
	
136
	lw $at,EOFFSET_AT(\r)
155
	lw $at,EOFFSET_AT(\r)
137
	lw $sp,EOFFSET_SP(\r)
156
	lw $sp,EOFFSET_SP(\r)
138
.endm
157
.endm
139
 
158
 
140
# Move kernel stack pointer address to register K0
159
# Move kernel stack pointer address to register K0
141
# - if we are in user mode, load the appropriate stack
160
# - if we are in user mode, load the appropriate stack
142
# address
161
# address
143
.macro KERNEL_STACK_TO_K0
162
.macro KERNEL_STACK_TO_K0
144
	# If we are in user mode
163
	# If we are in user mode
145
	mfc0 $k0, $status
164
	mfc0 $k0, $status
146
	andi $k0, 0x10
165
	andi $k0, 0x10
147
	
166
	
148
	beq $k0, $0, 1f
167
	beq $k0, $0, 1f
149
	add $k0, $sp, 0
168
	add $k0, $sp, 0
150
	
169
	
151
	# Move $k0 pointer to kernel stack
170
	# Move $k0 pointer to kernel stack
152
	lui $k0, %hi(supervisor_sp)
171
	lui $k0, %hi(supervisor_sp)
153
	ori $k0, $k0, %lo(supervisor_sp)
172
	ori $k0, $k0, %lo(supervisor_sp)
154
	# Move $k0 (superveisor_sp)
173
	# Move $k0 (superveisor_sp)
155
	lw $k0, 0($k0)
174
	lw $k0, 0($k0)
156
1:		
175
1:		
157
.endm
176
.endm
158
		
177
		
159
.org 0x0
178
.org 0x0
160
kernel_image_start:
179
kernel_image_start:
161
	/* Load temporary stack */
180
	/* Load temporary stack */
162
	lui $sp, %hi(end_stack)
181
	lui $sp, %hi(end_stack)
163
	ori $sp, $sp, %lo(end_stack)
182
	ori $sp, $sp, %lo(end_stack)
164
 
183
 
165
	/* Not sure about this, but might be needed for PIC code???? */
184
	/* Not sure about this, but might be needed for PIC code???? */
166
	lui $gp, 0x8000
185
	lui $gp, 0x8000
167
	
186
	
168
	jal main_bsp
187
	jal main_bsp
169
	nop
188
	nop
170
 
189
 
171
 
190
 
172
	.space TEMP_STACK_SIZE
191
	.space TEMP_STACK_SIZE
173
end_stack:
192
end_stack:
174
 
193
 
175
tlb_refill_entry:
194
tlb_refill_entry:
176
	j tlb_refill_handler
195
	j tlb_refill_handler
177
	nop
196
	nop
178
 
197
 
179
cache_error_entry:
198
cache_error_entry:
180
	j cache_error_handler
199
	j cache_error_handler
181
	nop
200
	nop
182
 
201
 
183
exception_entry:
202
exception_entry:
184
	j exception_handler
203
	j exception_handler
185
	nop	
204
	nop	
186
 
205
 
187
	
206
	
188
	
207
	
189
exception_handler:
208
exception_handler:
190
	KERNEL_STACK_TO_K0
209
	KERNEL_STACK_TO_K0
-
 
210
	
-
 
211
	mfc0 $k1, $cause
191
	sub $k0, REGISTER_SPACE
212
	sub $k0, REGISTER_SPACE
-
 
213
	
-
 
214
	sra $k1, $k1, 0x2     # cp0_exc_cause() part 1
-
 
215
	andi $k1, $k1, 0x1f   # cp0_exc_cause() part 2
-
 
216
	sub $k1, 8            # 8=SYSCALL
-
 
217
	
-
 
218
	beqz $k1, uspace_shortcut
-
 
219
	add $k1, 8            # Revert $k1 back to correct exc number
-
 
220
	
192
	REGISTERS_STORE $k0
221
	REGISTERS_STORE_AND_EXC_RESET $k0
193
	add $sp, $k0, 0
222
	move $sp, $k0
194
 
223
	
195
	add $a0, $sp, 0 
224
	move $a1, $sp
196
	jal exception /* exception(register_space) */
225
	jal exc_dispatch      # exc_dispatch(excno, register_space)
197
	nop
226
	move $a0, $k1
198
 
227
 
199
	REGISTERS_LOAD $sp
228
	REGISTERS_LOAD $sp
200
	# The $sp is automatically restored to former value
229
	# The $sp is automatically restored to former value
201
	eret
230
	eret
202
	nop
231
	nop
-
 
232
 
-
 
233
# it seems that mips reserves some space on stack for varfuncs???
-
 
234
#define SS_ARG4   16
-
 
235
#define SS_SP     20
-
 
236
#define SS_STATUS 24
-
 
237
#define SS_EPC    28
-
 
238
#define SS_RA     32
-
 
239
uspace_shortcut:
-
 
240
	# We have a lot of space on the stack, with free use
-
 
241
	sw $sp, SS_SP($k0)
-
 
242
	move $sp, $k0
-
 
243
	sw $ra, SS_RA($k0)
-
 
244
 
-
 
245
	mfc0 $t1, $epc
-
 
246
	mfc0 $t0, $status
-
 
247
	sw $t1,SS_EPC($sp)  # Save EPC
-
 
248
	
-
 
249
	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
-
 
250
	li $t3, ~(0x1f)
-
 
251
	and $t0, $t0, $t3           # Clear KSU,EXL,ERL
-
 
252
	ori $t0, $t0, 0x1           # Set IE
-
 
253
 
-
 
254
	sw $t2,SS_STATUS($sp)
-
 
255
	mtc0 $t0, $status
-
 
256
 
-
 
257
	jal syscall_handler
-
 
258
	sw $v0, SS_ARG4($sp)        # save v0 - arg4 to stack
-
 
259
 
-
 
260
	# Restore RA
-
 
261
	lw $ra, SS_RA($sp)
-
 
262
	
-
 
263
	# restore epc+4
-
 
264
	lw $t0,SS_EPC($sp)
-
 
265
	addi $t0, $t0, 4
-
 
266
	mtc0 $t0, $epc
-
 
267
	
-
 
268
	# restore status
-
 
269
	mfc0 $t0, $status
-
 
270
	lw $t1,SS_STATUS($sp)
-
 
271
 
-
 
272
	li $t2, ~REG_SAVE_MASK      # Mask UM,EXL,ERL,IE
-
 
273
	and $t0, $t0, $t2
-
 
274
	or $t0, $t0, $t1            # Copy UM,EXL,ERL,IE from saved status
-
 
275
	mtc0 $t0, $status
-
 
276
			
-
 
277
	lw $sp,SS_SP($sp) # restore sp
-
 
278
	
-
 
279
	eret
203
	
280
	
204
tlb_refill_handler:
281
tlb_refill_handler:
205
	KERNEL_STACK_TO_K0
282
	KERNEL_STACK_TO_K0
206
	sub $k0, REGISTER_SPACE
283
	sub $k0, REGISTER_SPACE
207
	REGISTERS_STORE $k0
284
	REGISTERS_STORE_AND_EXC_RESET $k0
208
	add $sp, $k0, 0
285
	add $sp, $k0, 0
209
 
286
 
210
	add $a0, $sp, 0 
287
	add $a0, $sp, 0 
211
	jal tlb_refill /* tlb_refill(register_space) */
288
	jal tlb_refill /* tlb_refill(register_space) */
212
	nop
289
	nop
213
 
290
 
214
	REGISTERS_LOAD $sp
291
	REGISTERS_LOAD $sp
215
 
292
 
216
	eret
293
	eret
217
	nop
-
 
218
 
294
 
219
cache_error_handler:
295
cache_error_handler:
220
	KERNEL_STACK_TO_K0
296
	KERNEL_STACK_TO_K0
221
	sub $sp, REGISTER_SPACE
297
	sub $sp, REGISTER_SPACE
222
	REGISTERS_STORE $sp
298
	REGISTERS_STORE_AND_EXC_RESET $sp
223
	add $sp, $k0, 0
299
	add $sp, $k0, 0
224
 
300
 
225
	jal cache_error
301
	jal cache_error
226
	nop
302
	nop
227
 
303
 
228
	REGISTERS_LOAD $sp
304
	REGISTERS_LOAD $sp
229
 
305
 
230
	eret
306
	eret
231
	nop
-
 
232
 
307
 
233
userspace_asm:
308
userspace_asm:
234
	add $sp, $a0, 0
309
	add $sp, $a0, 0
235
	add $v0, $a1, 0
310
	add $v0, $a1, 0
236
	eret
311
	eret
237
	nop
-
 
238
 
312
 
239
 
313