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| Rev 703 | Rev 704 | ||
|---|---|---|---|
| Line 397... | Line 397... | ||
| 397 | /** Print contents of TLB. */ |
397 | /** Print contents of TLB. */ |
| 398 | void tlb_print(void) |
398 | void tlb_print(void) |
| 399 | { |
399 | { |
| 400 | page_mask_t mask; |
400 | page_mask_t mask; |
| 401 | entry_lo_t lo0, lo1; |
401 | entry_lo_t lo0, lo1; |
| 402 | entry_hi_t hi; |
402 | entry_hi_t hi, hi_save; |
| 403 | int i; |
403 | int i; |
| 404 | 404 | ||
| - | 405 | hi_save.value = cp0_entry_hi_read(); |
|
| - | 406 | ||
| 405 | printf("TLB:\n"); |
407 | printf("TLB:\n"); |
| 406 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
408 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
| 407 | cp0_index_write(i); |
409 | cp0_index_write(i); |
| 408 | tlbr(); |
410 | tlbr(); |
| 409 | 411 | ||
| Line 415... | Line 417... | ||
| 415 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n" |
417 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n" |
| 416 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n", |
418 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n", |
| 417 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
419 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
| 418 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
420 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
| 419 | } |
421 | } |
| - | 422 | ||
| - | 423 | cp0_entry_hi_write(hi_save.value); |
|
| 420 | } |
424 | } |
| 421 | 425 | ||
| 422 | /** Invalidate all not wired TLB entries. */ |
426 | /** Invalidate all not wired TLB entries. */ |
| 423 | void tlb_invalidate_all(void) |
427 | void tlb_invalidate_all(void) |
| 424 | { |
428 | { |
| 425 | ipl_t ipl; |
429 | ipl_t ipl; |
| 426 | entry_lo_t lo0, lo1; |
430 | entry_lo_t lo0, lo1; |
| - | 431 | entry_hi_t hi_save; |
|
| 427 | int i; |
432 | int i; |
| 428 | 433 | ||
| - | 434 | hi_save.value = cp0_entry_hi_read(); |
|
| 429 | ipl = interrupts_disable(); |
435 | ipl = interrupts_disable(); |
| 430 | 436 | ||
| 431 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
437 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
| 432 | cp0_index_write(i); |
438 | cp0_index_write(i); |
| 433 | tlbr(); |
439 | tlbr(); |
| Line 443... | Line 449... | ||
| 443 | 449 | ||
| 444 | tlbwi(); |
450 | tlbwi(); |
| 445 | } |
451 | } |
| 446 | 452 | ||
| 447 | interrupts_restore(ipl); |
453 | interrupts_restore(ipl); |
| - | 454 | cp0_entry_hi_write(hi_save.value); |
|
| 448 | } |
455 | } |
| 449 | 456 | ||
| 450 | /** Invalidate all TLB entries belonging to specified address space. |
457 | /** Invalidate all TLB entries belonging to specified address space. |
| 451 | * |
458 | * |
| 452 | * @param asid Address space identifier. |
459 | * @param asid Address space identifier. |
| 453 | */ |
460 | */ |
| 454 | void tlb_invalidate_asid(asid_t asid) |
461 | void tlb_invalidate_asid(asid_t asid) |
| 455 | { |
462 | { |
| 456 | ipl_t ipl; |
463 | ipl_t ipl; |
| 457 | entry_lo_t lo0, lo1; |
464 | entry_lo_t lo0, lo1; |
| 458 | entry_hi_t hi; |
465 | entry_hi_t hi, hi_save; |
| 459 | int i; |
466 | int i; |
| 460 | 467 | ||
| 461 | ASSERT(asid != ASID_INVALID); |
468 | ASSERT(asid != ASID_INVALID); |
| 462 | 469 | ||
| - | 470 | hi_save.value = cp0_entry_hi_read(); |
|
| 463 | ipl = interrupts_disable(); |
471 | ipl = interrupts_disable(); |
| 464 | 472 | ||
| 465 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
473 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
| 466 | cp0_index_write(i); |
474 | cp0_index_write(i); |
| 467 | tlbr(); |
475 | tlbr(); |
| Line 481... | Line 489... | ||
| 481 | tlbwi(); |
489 | tlbwi(); |
| 482 | } |
490 | } |
| 483 | } |
491 | } |
| 484 | 492 | ||
| 485 | interrupts_restore(ipl); |
493 | interrupts_restore(ipl); |
| - | 494 | cp0_entry_hi_write(hi_save.value); |
|
| 486 | } |
495 | } |
| 487 | 496 | ||
| 488 | /** Invalidate TLB entry for specified page belonging to specified address space. |
497 | /** Invalidate TLB entry for specified page belonging to specified address space. |
| 489 | * |
498 | * |
| 490 | * @param asid Address space identifier. |
499 | * @param asid Address space identifier. |
| Line 492... | Line 501... | ||
| 492 | */ |
501 | */ |
| 493 | void tlb_invalidate_page(asid_t asid, __address page) |
502 | void tlb_invalidate_page(asid_t asid, __address page) |
| 494 | { |
503 | { |
| 495 | ipl_t ipl; |
504 | ipl_t ipl; |
| 496 | entry_lo_t lo0, lo1; |
505 | entry_lo_t lo0, lo1; |
| 497 | entry_hi_t hi; |
506 | entry_hi_t hi, hi_save; |
| 498 | tlb_index_t index; |
507 | tlb_index_t index; |
| 499 | 508 | ||
| 500 | ASSERT(asid != ASID_INVALID); |
509 | ASSERT(asid != ASID_INVALID); |
| 501 | 510 | ||
| - | 511 | hi_save.value = cp0_entry_hi_read(); |
|
| 502 | ipl = interrupts_disable(); |
512 | ipl = interrupts_disable(); |
| 503 | 513 | ||
| 504 | hi.value = 0; |
514 | hi.value = 0; |
| 505 | prepare_entry_hi(&hi, asid, page); |
515 | prepare_entry_hi(&hi, asid, page); |
| 506 | cp0_entry_hi_write(hi.value); |
516 | cp0_entry_hi_write(hi.value); |
| Line 523... | Line 533... | ||
| 523 | 533 | ||
| 524 | tlbwi(); |
534 | tlbwi(); |
| 525 | } |
535 | } |
| 526 | 536 | ||
| 527 | interrupts_restore(ipl); |
537 | interrupts_restore(ipl); |
| - | 538 | cp0_entry_hi_write(hi_save.value); |
|
| 528 | } |
539 | } |