WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm   
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
 
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
 
static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);
    asid = AS->asid;
    spinlock_unlock(&AS->lock);
 
    page_table_lock(AS, true);
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_hi(&hi, asid, badvaddr);
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->ra);
    if (s)
        sym2 = s;
 
    fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 * @param access Access mode that caused the fault.
 * @param istate Pointer to interrupted state.
 * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
            printf("Page fault.\n");
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("unexpected rc (%d)\n", rc);
        }
       
    }
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
 
    printf("TLB:\n");
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
               "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
               i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
               lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt+1; i+=2) {
        hi.value = 0;
        prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /* Entry was found, index register contains valid index. */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** @}
 */
 

Rev 1776	Rev 1780
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/asid.h>	36	#include <mm/asid.h>
37	#include <mm/tlb.h>	37	#include <mm/tlb.h>
38	#include <mm/page.h>	38	#include <mm/page.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/cp0.h>	40	#include <arch/cp0.h>
41	#include <panic.h>	41	#include <panic.h>
42	#include <arch.h>	42	#include <arch.h>
43	#include <symtab.h>	43	#include <symtab.h>
44	#include <synch/spinlock.h>	44	#include <synch/spinlock.h>
45	#include <print.h>	45	#include <print.h>
46	#include <debug.h>	46	#include <debug.h>
47	#include <align.h>	47	#include <align.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49		49
50	static void tlb_refill_fail(istate_t *istate);	50	static void tlb_refill_fail(istate_t *istate);
51	static void tlb_invalid_fail(istate_t *istate);	51	static void tlb_invalid_fail(istate_t *istate);
52	static void tlb_modified_fail(istate_t *istate);	52	static void tlb_modified_fail(istate_t *istate);
53		53
54	static pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc);	54	static pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc);
55		55
56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);	56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
58		58
59	/** Initialize TLB	59	/** Initialize TLB
60	*	60	*
61	* Initialize TLB.	61	* Initialize TLB.
62	* Invalidate all entries and mark wired entries.	62	* Invalidate all entries and mark wired entries.
63	*/	63	*/
64	void tlb_arch_init(void)	64	void tlb_arch_init(void)
65	{	65	{
66	int i;	66	int i;
67		67
68	cp0_pagemask_write(TLB_PAGE_MASK_16K);	68	cp0_pagemask_write(TLB_PAGE_MASK_16K);
69	cp0_entry_hi_write(0);	69	cp0_entry_hi_write(0);
70	cp0_entry_lo0_write(0);	70	cp0_entry_lo0_write(0);
71	cp0_entry_lo1_write(0);	71	cp0_entry_lo1_write(0);
72		72
73	/* Clear and initialize TLB. */	73	/* Clear and initialize TLB. */
74		74
75	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	75	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
76	cp0_index_write(i);	76	cp0_index_write(i);
77	tlbwi();	77	tlbwi();
78	}	78	}
79		79
80		80
81	/*	81	/*
82	* The kernel is going to make use of some wired	82	* The kernel is going to make use of some wired
83	* entries (e.g. mapping kernel stacks in kseg3).	83	* entries (e.g. mapping kernel stacks in kseg3).
84	*/	84	*/
85	cp0_wired_write(TLB_WIRED);	85	cp0_wired_write(TLB_WIRED);
86	}	86	}
87		87
88	/** Process TLB Refill Exception	88	/** Process TLB Refill Exception
89	*	89	*
90	* Process TLB Refill Exception.	90	* Process TLB Refill Exception.
91	*	91	*
92	* @param istate Interrupted register context.	92	* @param istate Interrupted register context.
93	*/	93	*/
94	void tlb_refill(istate_t *istate)	94	void tlb_refill(istate_t *istate)
95	{	95	{
96	entry_lo_t lo;	96	entry_lo_t lo;
97	entry_hi_t hi;	97	entry_hi_t hi;
98	asid_t asid;	98	asid_t asid;
99	__address badvaddr;	99	uintptr_t badvaddr;
100	pte_t *pte;	100	pte_t *pte;
101	int pfrc;	101	int pfrc;
102		102
103	badvaddr = cp0_badvaddr_read();	103	badvaddr = cp0_badvaddr_read();
104		104
105	spinlock_lock(&AS->lock);	105	spinlock_lock(&AS->lock);
106	asid = AS->asid;	106	asid = AS->asid;
107	spinlock_unlock(&AS->lock);	107	spinlock_unlock(&AS->lock);
108		108
109	page_table_lock(AS, true);	109	page_table_lock(AS, true);
110		110
111	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	111	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
112	if (!pte) {	112	if (!pte) {
113	switch (pfrc) {	113	switch (pfrc) {
114	case AS_PF_FAULT:	114	case AS_PF_FAULT:
115	goto fail;	115	goto fail;
116	break;	116	break;
117	case AS_PF_DEFER:	117	case AS_PF_DEFER:
118	/*	118	/*
119	* The page fault came during copy_from_uspace()	119	* The page fault came during copy_from_uspace()
120	* or copy_to_uspace().	120	* or copy_to_uspace().
121	*/	121	*/
122	page_table_unlock(AS, true);	122	page_table_unlock(AS, true);
123	return;	123	return;
124	default:	124	default:
125	panic("unexpected pfrc (%d)\n", pfrc);	125	panic("unexpected pfrc (%d)\n", pfrc);
126	}	126	}
127	}	127	}
128		128
129	/*	129	/*
130	* Record access to PTE.	130	* Record access to PTE.
131	*/	131	*/
132	pte->a = 1;	132	pte->a = 1;
133		133
134	prepare_entry_hi(&hi, asid, badvaddr);	134	prepare_entry_hi(&hi, asid, badvaddr);
135	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	135	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
136		136
137	/*	137	/*
138	* New entry is to be inserted into TLB	138	* New entry is to be inserted into TLB
139	*/	139	*/
140	cp0_entry_hi_write(hi.value);	140	cp0_entry_hi_write(hi.value);
141	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	141	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
142	cp0_entry_lo0_write(lo.value);	142	cp0_entry_lo0_write(lo.value);
143	cp0_entry_lo1_write(0);	143	cp0_entry_lo1_write(0);
144	}	144	}
145	else {	145	else {
146	cp0_entry_lo0_write(0);	146	cp0_entry_lo0_write(0);
147	cp0_entry_lo1_write(lo.value);	147	cp0_entry_lo1_write(lo.value);
148	}	148	}
149	cp0_pagemask_write(TLB_PAGE_MASK_16K);	149	cp0_pagemask_write(TLB_PAGE_MASK_16K);
150	tlbwr();	150	tlbwr();
151		151
152	page_table_unlock(AS, true);	152	page_table_unlock(AS, true);
153	return;	153	return;
154		154
155	fail:	155	fail:
156	page_table_unlock(AS, true);	156	page_table_unlock(AS, true);
157	tlb_refill_fail(istate);	157	tlb_refill_fail(istate);
158	}	158	}
159		159
160	/** Process TLB Invalid Exception	160	/** Process TLB Invalid Exception
161	*	161	*
162	* Process TLB Invalid Exception.	162	* Process TLB Invalid Exception.
163	*	163	*
164	* @param istate Interrupted register context.	164	* @param istate Interrupted register context.
165	*/	165	*/
166	void tlb_invalid(istate_t *istate)	166	void tlb_invalid(istate_t *istate)
167	{	167	{
168	tlb_index_t index;	168	tlb_index_t index;
169	__address badvaddr;	169	uintptr_t badvaddr;
170	entry_lo_t lo;	170	entry_lo_t lo;
171	entry_hi_t hi;	171	entry_hi_t hi;
172	pte_t *pte;	172	pte_t *pte;
173	int pfrc;	173	int pfrc;
174		174
175	badvaddr = cp0_badvaddr_read();	175	badvaddr = cp0_badvaddr_read();
176		176
177	/*	177	/*
178	* Locate the faulting entry in TLB.	178	* Locate the faulting entry in TLB.
179	*/	179	*/
180	hi.value = cp0_entry_hi_read();	180	hi.value = cp0_entry_hi_read();
181	prepare_entry_hi(&hi, hi.asid, badvaddr);	181	prepare_entry_hi(&hi, hi.asid, badvaddr);
182	cp0_entry_hi_write(hi.value);	182	cp0_entry_hi_write(hi.value);
183	tlbp();	183	tlbp();
184	index.value = cp0_index_read();	184	index.value = cp0_index_read();
185		185
186	page_table_lock(AS, true);	186	page_table_lock(AS, true);
187		187
188	/*	188	/*
189	* Fail if the entry is not in TLB.	189	* Fail if the entry is not in TLB.
190	*/	190	*/
191	if (index.p) {	191	if (index.p) {
192	printf("TLB entry not found.\n");	192	printf("TLB entry not found.\n");
193	goto fail;	193	goto fail;
194	}	194	}
195		195
196	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	196	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
197	if (!pte) {	197	if (!pte) {
198	switch (pfrc) {	198	switch (pfrc) {
199	case AS_PF_FAULT:	199	case AS_PF_FAULT:
200	goto fail;	200	goto fail;
201	break;	201	break;
202	case AS_PF_DEFER:	202	case AS_PF_DEFER:
203	/*	203	/*
204	* The page fault came during copy_from_uspace()	204	* The page fault came during copy_from_uspace()
205	* or copy_to_uspace().	205	* or copy_to_uspace().
206	*/	206	*/
207	page_table_unlock(AS, true);	207	page_table_unlock(AS, true);
208	return;	208	return;
209	default:	209	default:
210	panic("unexpected pfrc (%d)\n", pfrc);	210	panic("unexpected pfrc (%d)\n", pfrc);
211	}	211	}
212	}	212	}
213		213
214	/*	214	/*
215	* Read the faulting TLB entry.	215	* Read the faulting TLB entry.
216	*/	216	*/
217	tlbr();	217	tlbr();
218		218
219	/*	219	/*
220	* Record access to PTE.	220	* Record access to PTE.
221	*/	221	*/
222	pte->a = 1;	222	pte->a = 1;
223		223
224	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	224	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
225		225
226	/*	226	/*
227	* The entry is to be updated in TLB.	227	* The entry is to be updated in TLB.
228	*/	228	*/
229	if ((badvaddr/PAGE_SIZE) % 2 == 0)	229	if ((badvaddr/PAGE_SIZE) % 2 == 0)
230	cp0_entry_lo0_write(lo.value);	230	cp0_entry_lo0_write(lo.value);
231	else	231	else
232	cp0_entry_lo1_write(lo.value);	232	cp0_entry_lo1_write(lo.value);
233	cp0_pagemask_write(TLB_PAGE_MASK_16K);	233	cp0_pagemask_write(TLB_PAGE_MASK_16K);
234	tlbwi();	234	tlbwi();
235		235
236	page_table_unlock(AS, true);	236	page_table_unlock(AS, true);
237	return;	237	return;
238		238
239	fail:	239	fail:
240	page_table_unlock(AS, true);	240	page_table_unlock(AS, true);
241	tlb_invalid_fail(istate);	241	tlb_invalid_fail(istate);
242	}	242	}
243		243
244	/** Process TLB Modified Exception	244	/** Process TLB Modified Exception
245	*	245	*
246	* Process TLB Modified Exception.	246	* Process TLB Modified Exception.
247	*	247	*
248	* @param istate Interrupted register context.	248	* @param istate Interrupted register context.
249	*/	249	*/
250	void tlb_modified(istate_t *istate)	250	void tlb_modified(istate_t *istate)
251	{	251	{
252	tlb_index_t index;	252	tlb_index_t index;
253	__address badvaddr;	253	uintptr_t badvaddr;
254	entry_lo_t lo;	254	entry_lo_t lo;
255	entry_hi_t hi;	255	entry_hi_t hi;
256	pte_t *pte;	256	pte_t *pte;
257	int pfrc;	257	int pfrc;
258		258
259	badvaddr = cp0_badvaddr_read();	259	badvaddr = cp0_badvaddr_read();
260		260
261	/*	261	/*
262	* Locate the faulting entry in TLB.	262	* Locate the faulting entry in TLB.
263	*/	263	*/
264	hi.value = cp0_entry_hi_read();	264	hi.value = cp0_entry_hi_read();
265	prepare_entry_hi(&hi, hi.asid, badvaddr);	265	prepare_entry_hi(&hi, hi.asid, badvaddr);
266	cp0_entry_hi_write(hi.value);	266	cp0_entry_hi_write(hi.value);
267	tlbp();	267	tlbp();
268	index.value = cp0_index_read();	268	index.value = cp0_index_read();
269		269
270	page_table_lock(AS, true);	270	page_table_lock(AS, true);
271		271
272	/*	272	/*
273	* Fail if the entry is not in TLB.	273	* Fail if the entry is not in TLB.
274	*/	274	*/
275	if (index.p) {	275	if (index.p) {
276	printf("TLB entry not found.\n");	276	printf("TLB entry not found.\n");
277	goto fail;	277	goto fail;
278	}	278	}
279		279
280	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);	280	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
281	if (!pte) {	281	if (!pte) {
282	switch (pfrc) {	282	switch (pfrc) {
283	case AS_PF_FAULT:	283	case AS_PF_FAULT:
284	goto fail;	284	goto fail;
285	break;	285	break;
286	case AS_PF_DEFER:	286	case AS_PF_DEFER:
287	/*	287	/*
288	* The page fault came during copy_from_uspace()	288	* The page fault came during copy_from_uspace()
289	* or copy_to_uspace().	289	* or copy_to_uspace().
290	*/	290	*/
291	page_table_unlock(AS, true);	291	page_table_unlock(AS, true);
292	return;	292	return;
293	default:	293	default:
294	panic("unexpected pfrc (%d)\n", pfrc);	294	panic("unexpected pfrc (%d)\n", pfrc);
295	}	295	}
296	}	296	}
297		297
298	/*	298	/*
299	* Fail if the page is not writable.	299	* Fail if the page is not writable.
300	*/	300	*/
301	if (!pte->w)	301	if (!pte->w)
302	goto fail;	302	goto fail;
303		303
304	/*	304	/*
305	* Read the faulting TLB entry.	305	* Read the faulting TLB entry.
306	*/	306	*/
307	tlbr();	307	tlbr();
308		308
309	/*	309	/*
310	* Record access and write to PTE.	310	* Record access and write to PTE.
311	*/	311	*/
312	pte->a = 1;	312	pte->a = 1;
313	pte->d = 1;	313	pte->d = 1;
314		314
315	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);	315	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
316		316
317	/*	317	/*
318	* The entry is to be updated in TLB.	318	* The entry is to be updated in TLB.
319	*/	319	*/
320	if ((badvaddr/PAGE_SIZE) % 2 == 0)	320	if ((badvaddr/PAGE_SIZE) % 2 == 0)
321	cp0_entry_lo0_write(lo.value);	321	cp0_entry_lo0_write(lo.value);
322	else	322	else
323	cp0_entry_lo1_write(lo.value);	323	cp0_entry_lo1_write(lo.value);
324	cp0_pagemask_write(TLB_PAGE_MASK_16K);	324	cp0_pagemask_write(TLB_PAGE_MASK_16K);
325	tlbwi();	325	tlbwi();
326		326
327	page_table_unlock(AS, true);	327	page_table_unlock(AS, true);
328	return;	328	return;
329		329
330	fail:	330	fail:
331	page_table_unlock(AS, true);	331	page_table_unlock(AS, true);
332	tlb_modified_fail(istate);	332	tlb_modified_fail(istate);
333	}	333	}
334		334
335	void tlb_refill_fail(istate_t *istate)	335	void tlb_refill_fail(istate_t *istate)
336	{	336	{
337	char *symbol = "";	337	char *symbol = "";
338	char *sym2 = "";	338	char *sym2 = "";
339		339
340	char *s = get_symtab_entry(istate->epc);	340	char *s = get_symtab_entry(istate->epc);
341	if (s)	341	if (s)
342	symbol = s;	342	symbol = s;
343	s = get_symtab_entry(istate->ra);	343	s = get_symtab_entry(istate->ra);
344	if (s)	344	if (s)
345	sym2 = s;	345	sym2 = s;
346		346
347	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());	347	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
348	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);	348	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
349	}	349	}
350		350
351		351
352	void tlb_invalid_fail(istate_t *istate)	352	void tlb_invalid_fail(istate_t *istate)
353	{	353	{
354	char *symbol = "";	354	char *symbol = "";
355		355
356	char *s = get_symtab_entry(istate->epc);	356	char *s = get_symtab_entry(istate->epc);
357	if (s)	357	if (s)
358	symbol = s;	358	symbol = s;
359	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());	359	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
360	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	360	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
361	}	361	}
362		362
363	void tlb_modified_fail(istate_t *istate)	363	void tlb_modified_fail(istate_t *istate)
364	{	364	{
365	char *symbol = "";	365	char *symbol = "";
366		366
367	char *s = get_symtab_entry(istate->epc);	367	char *s = get_symtab_entry(istate->epc);
368	if (s)	368	if (s)
369	symbol = s;	369	symbol = s;
370	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());	370	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
371	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	371	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
372	}	372	}
373		373
374	/** Try to find PTE for faulting address	374	/** Try to find PTE for faulting address
375	*	375	*
376	* Try to find PTE for faulting address.	376	* Try to find PTE for faulting address.
377	* The AS->lock must be held on entry to this function.	377	* The AS->lock must be held on entry to this function.
378	*	378	*
379	* @param badvaddr Faulting virtual address.	379	* @param badvaddr Faulting virtual address.
380	* @param access Access mode that caused the fault.	380	* @param access Access mode that caused the fault.
381	* @param istate Pointer to interrupted state.	381	* @param istate Pointer to interrupted state.
382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
383	*	383	*
384	* @return PTE on success, NULL otherwise.	384	* @return PTE on success, NULL otherwise.
385	*/	385	*/
386	pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc)	386	pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc)
387	{	387	{
388	entry_hi_t hi;	388	entry_hi_t hi;
389	pte_t *pte;	389	pte_t *pte;
390		390
391	hi.value = cp0_entry_hi_read();	391	hi.value = cp0_entry_hi_read();
392		392
393	/*	393	/*
394	* Handler cannot succeed if the ASIDs don't match.	394	* Handler cannot succeed if the ASIDs don't match.
395	*/	395	*/
396	if (hi.asid != AS->asid) {	396	if (hi.asid != AS->asid) {
397	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	397	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
398	return NULL;	398	return NULL;
399	}	399	}
400		400
401	/*	401	/*
402	* Check if the mapping exists in page tables.	402	* Check if the mapping exists in page tables.
403	*/	403	*/
404	pte = page_mapping_find(AS, badvaddr);	404	pte = page_mapping_find(AS, badvaddr);
405	if (pte && pte->p) {	405	if (pte && pte->p) {
406	/*	406	/*
407	* Mapping found in page tables.	407	* Mapping found in page tables.
408	* Immediately succeed.	408	* Immediately succeed.
409	*/	409	*/
410	return pte;	410	return pte;
411	} else {	411	} else {
412	int rc;	412	int rc;
413		413
414	/*	414	/*
415	* Mapping not found in page tables.	415	* Mapping not found in page tables.
416	* Resort to higher-level page fault handler.	416	* Resort to higher-level page fault handler.
417	*/	417	*/
418	page_table_unlock(AS, true);	418	page_table_unlock(AS, true);
419	switch (rc = as_page_fault(badvaddr, access, istate)) {	419	switch (rc = as_page_fault(badvaddr, access, istate)) {
420	case AS_PF_OK:	420	case AS_PF_OK:
421	/*	421	/*
422	* The higher-level page fault handler succeeded,	422	* The higher-level page fault handler succeeded,
423	* The mapping ought to be in place.	423	* The mapping ought to be in place.
424	*/	424	*/
425	page_table_lock(AS, true);	425	page_table_lock(AS, true);
426	pte = page_mapping_find(AS, badvaddr);	426	pte = page_mapping_find(AS, badvaddr);
427	ASSERT(pte && pte->p);	427	ASSERT(pte && pte->p);
428	return pte;	428	return pte;
429	break;	429	break;
430	case AS_PF_DEFER:	430	case AS_PF_DEFER:
431	page_table_lock(AS, true);	431	page_table_lock(AS, true);
432	*pfrc = AS_PF_DEFER;	432	*pfrc = AS_PF_DEFER;
433	return NULL;	433	return NULL;
434	break;	434	break;
435	case AS_PF_FAULT:	435	case AS_PF_FAULT:
436	page_table_lock(AS, true);	436	page_table_lock(AS, true);
437	printf("Page fault.\n");	437	printf("Page fault.\n");
438	*pfrc = AS_PF_FAULT;	438	*pfrc = AS_PF_FAULT;
439	return NULL;	439	return NULL;
440	break;	440	break;
441	default:	441	default:
442	panic("unexpected rc (%d)\n", rc);	442	panic("unexpected rc (%d)\n", rc);
443	}	443	}
444		444
445	}	445	}
446	}	446	}
447		447
448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)	448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
449	{	449	{
450	lo->value = 0;	450	lo->value = 0;
451	lo->g = g;	451	lo->g = g;
452	lo->v = v;	452	lo->v = v;
453	lo->d = d;	453	lo->d = d;
454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
455	lo->pfn = pfn;	455	lo->pfn = pfn;
456	}	456	}
457		457
458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
459	{	459	{
460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
461	hi->asid = asid;	461	hi->asid = asid;
462	}	462	}
463		463
464	/** Print contents of TLB. */	464	/** Print contents of TLB. */
465	void tlb_print(void)	465	void tlb_print(void)
466	{	466	{
467	page_mask_t mask;	467	page_mask_t mask;
468	entry_lo_t lo0, lo1;	468	entry_lo_t lo0, lo1;
469	entry_hi_t hi, hi_save;	469	entry_hi_t hi, hi_save;
470	int i;	470	int i;
471		471
472	hi_save.value = cp0_entry_hi_read();	472	hi_save.value = cp0_entry_hi_read();
473		473
474	printf("TLB:\n");	474	printf("TLB:\n");
475	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	475	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
476	cp0_index_write(i);	476	cp0_index_write(i);
477	tlbr();	477	tlbr();
478		478
479	mask.value = cp0_pagemask_read();	479	mask.value = cp0_pagemask_read();
480	hi.value = cp0_entry_hi_read();	480	hi.value = cp0_entry_hi_read();
481	lo0.value = cp0_entry_lo0_read();	481	lo0.value = cp0_entry_lo0_read();
482	lo1.value = cp0_entry_lo1_read();	482	lo1.value = cp0_entry_lo1_read();
483		483
484	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"	484	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
485	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",	485	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
486	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,	486	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
487	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	487	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
488	}	488	}
489		489
490	cp0_entry_hi_write(hi_save.value);	490	cp0_entry_hi_write(hi_save.value);
491	}	491	}
492		492
493	/** Invalidate all not wired TLB entries. */	493	/** Invalidate all not wired TLB entries. */
494	void tlb_invalidate_all(void)	494	void tlb_invalidate_all(void)
495	{	495	{
496	ipl_t ipl;	496	ipl_t ipl;
497	entry_lo_t lo0, lo1;	497	entry_lo_t lo0, lo1;
498	entry_hi_t hi_save;	498	entry_hi_t hi_save;
499	int i;	499	int i;
500		500

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(root)/kernel/trunk/arch/mips32/src/mm/tlb.c – Rev 1776 → 1780