WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup mips32mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
 
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
 
static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    __address badvaddr;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);
    asid = AS->asid;
    spinlock_unlock(&AS->lock);
 
    page_table_lock(AS, true);
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_hi(&hi, asid, badvaddr);
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->ra);
    if (s)
        sym2 = s;
 
    fault_if_from_uspace(istate, "TLB Refill Exception on %P", cp0_badvaddr_read());
    panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Invalid Exception on %P", cp0_badvaddr_read());
    panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Modified Exception on %P", cp0_badvaddr_read());
    panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 * @param access Access mode that caused the fault.
 * @param istate Pointer to interrupted state.
 * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
            printf("Page fault.\n");
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("unexpected rc (%d)\n", rc);
        }
       
    }
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
 
    printf("TLB:\n");
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
               "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
               i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
               lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt+1; i+=2) {
        hi.value = 0;
        prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /* Entry was found, index register contains valid index. */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
 /** @}
 */
 
 

Rev 1595	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup mips32mm
-		30	* @{
-		31	*/
-		32	/** @file
-		33	*/
-		34
29	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
30	#include <mm/asid.h>	36	#include <mm/asid.h>
31	#include <mm/tlb.h>	37	#include <mm/tlb.h>
32	#include <mm/page.h>	38	#include <mm/page.h>
33	#include <mm/as.h>	39	#include <mm/as.h>
34	#include <arch/cp0.h>	40	#include <arch/cp0.h>
35	#include <panic.h>	41	#include <panic.h>
36	#include <arch.h>	42	#include <arch.h>
37	#include <symtab.h>	43	#include <symtab.h>
38	#include <synch/spinlock.h>	44	#include <synch/spinlock.h>
39	#include <print.h>	45	#include <print.h>
40	#include <debug.h>	46	#include <debug.h>
41	#include <align.h>	47	#include <align.h>
42	#include <interrupt.h>	48	#include <interrupt.h>
43		49
44	static void tlb_refill_fail(istate_t *istate);	50	static void tlb_refill_fail(istate_t *istate);
45	static void tlb_invalid_fail(istate_t *istate);	51	static void tlb_invalid_fail(istate_t *istate);
46	static void tlb_modified_fail(istate_t *istate);	52	static void tlb_modified_fail(istate_t *istate);
47		53
48	static pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc);	54	static pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc);
49		55
50	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);	56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
51	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
52		58
53	/** Initialize TLB	59	/** Initialize TLB
54	*	60	*
55	* Initialize TLB.	61	* Initialize TLB.
56	* Invalidate all entries and mark wired entries.	62	* Invalidate all entries and mark wired entries.
57	*/	63	*/
58	void tlb_arch_init(void)	64	void tlb_arch_init(void)
59	{	65	{
60	int i;	66	int i;
61		67
62	cp0_pagemask_write(TLB_PAGE_MASK_16K);	68	cp0_pagemask_write(TLB_PAGE_MASK_16K);
63	cp0_entry_hi_write(0);	69	cp0_entry_hi_write(0);
64	cp0_entry_lo0_write(0);	70	cp0_entry_lo0_write(0);
65	cp0_entry_lo1_write(0);	71	cp0_entry_lo1_write(0);
66		72
67	/* Clear and initialize TLB. */	73	/* Clear and initialize TLB. */
68		74
69	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	75	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
70	cp0_index_write(i);	76	cp0_index_write(i);
71	tlbwi();	77	tlbwi();
72	}	78	}
73		79
74		80
75	/*	81	/*
76	* The kernel is going to make use of some wired	82	* The kernel is going to make use of some wired
77	* entries (e.g. mapping kernel stacks in kseg3).	83	* entries (e.g. mapping kernel stacks in kseg3).
78	*/	84	*/
79	cp0_wired_write(TLB_WIRED);	85	cp0_wired_write(TLB_WIRED);
80	}	86	}
81		87
82	/** Process TLB Refill Exception	88	/** Process TLB Refill Exception
83	*	89	*
84	* Process TLB Refill Exception.	90	* Process TLB Refill Exception.
85	*	91	*
86	* @param istate Interrupted register context.	92	* @param istate Interrupted register context.
87	*/	93	*/
88	void tlb_refill(istate_t *istate)	94	void tlb_refill(istate_t *istate)
89	{	95	{
90	entry_lo_t lo;	96	entry_lo_t lo;
91	entry_hi_t hi;	97	entry_hi_t hi;
92	asid_t asid;	98	asid_t asid;
93	__address badvaddr;	99	__address badvaddr;
94	pte_t *pte;	100	pte_t *pte;
95	int pfrc;	101	int pfrc;
96		102
97	badvaddr = cp0_badvaddr_read();	103	badvaddr = cp0_badvaddr_read();
98		104
99	spinlock_lock(&AS->lock);	105	spinlock_lock(&AS->lock);
100	asid = AS->asid;	106	asid = AS->asid;
101	spinlock_unlock(&AS->lock);	107	spinlock_unlock(&AS->lock);
102		108
103	page_table_lock(AS, true);	109	page_table_lock(AS, true);
104		110
105	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	111	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
106	if (!pte) {	112	if (!pte) {
107	switch (pfrc) {	113	switch (pfrc) {
108	case AS_PF_FAULT:	114	case AS_PF_FAULT:
109	goto fail;	115	goto fail;
110	break;	116	break;
111	case AS_PF_DEFER:	117	case AS_PF_DEFER:
112	/*	118	/*
113	* The page fault came during copy_from_uspace()	119	* The page fault came during copy_from_uspace()
114	* or copy_to_uspace().	120	* or copy_to_uspace().
115	*/	121	*/
116	page_table_unlock(AS, true);	122	page_table_unlock(AS, true);
117	return;	123	return;
118	default:	124	default:
119	panic("unexpected pfrc (%d)\n", pfrc);	125	panic("unexpected pfrc (%d)\n", pfrc);
120	}	126	}
121	}	127	}
122		128
123	/*	129	/*
124	* Record access to PTE.	130	* Record access to PTE.
125	*/	131	*/
126	pte->a = 1;	132	pte->a = 1;
127		133
128	prepare_entry_hi(&hi, asid, badvaddr);	134	prepare_entry_hi(&hi, asid, badvaddr);
129	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	135	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
130		136
131	/*	137	/*
132	* New entry is to be inserted into TLB	138	* New entry is to be inserted into TLB
133	*/	139	*/
134	cp0_entry_hi_write(hi.value);	140	cp0_entry_hi_write(hi.value);
135	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	141	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
136	cp0_entry_lo0_write(lo.value);	142	cp0_entry_lo0_write(lo.value);
137	cp0_entry_lo1_write(0);	143	cp0_entry_lo1_write(0);
138	}	144	}
139	else {	145	else {
140	cp0_entry_lo0_write(0);	146	cp0_entry_lo0_write(0);
141	cp0_entry_lo1_write(lo.value);	147	cp0_entry_lo1_write(lo.value);
142	}	148	}
143	cp0_pagemask_write(TLB_PAGE_MASK_16K);	149	cp0_pagemask_write(TLB_PAGE_MASK_16K);
144	tlbwr();	150	tlbwr();
145		151
146	page_table_unlock(AS, true);	152	page_table_unlock(AS, true);
147	return;	153	return;
148		154
149	fail:	155	fail:
150	page_table_unlock(AS, true);	156	page_table_unlock(AS, true);
151	tlb_refill_fail(istate);	157	tlb_refill_fail(istate);
152	}	158	}
153		159
154	/** Process TLB Invalid Exception	160	/** Process TLB Invalid Exception
155	*	161	*
156	* Process TLB Invalid Exception.	162	* Process TLB Invalid Exception.
157	*	163	*
158	* @param istate Interrupted register context.	164	* @param istate Interrupted register context.
159	*/	165	*/
160	void tlb_invalid(istate_t *istate)	166	void tlb_invalid(istate_t *istate)
161	{	167	{
162	tlb_index_t index;	168	tlb_index_t index;
163	__address badvaddr;	169	__address badvaddr;
164	entry_lo_t lo;	170	entry_lo_t lo;
165	entry_hi_t hi;	171	entry_hi_t hi;
166	pte_t *pte;	172	pte_t *pte;
167	int pfrc;	173	int pfrc;
168		174
169	badvaddr = cp0_badvaddr_read();	175	badvaddr = cp0_badvaddr_read();
170		176
171	/*	177	/*
172	* Locate the faulting entry in TLB.	178	* Locate the faulting entry in TLB.
173	*/	179	*/
174	hi.value = cp0_entry_hi_read();	180	hi.value = cp0_entry_hi_read();
175	prepare_entry_hi(&hi, hi.asid, badvaddr);	181	prepare_entry_hi(&hi, hi.asid, badvaddr);
176	cp0_entry_hi_write(hi.value);	182	cp0_entry_hi_write(hi.value);
177	tlbp();	183	tlbp();
178	index.value = cp0_index_read();	184	index.value = cp0_index_read();
179		185
180	page_table_lock(AS, true);	186	page_table_lock(AS, true);
181		187
182	/*	188	/*
183	* Fail if the entry is not in TLB.	189	* Fail if the entry is not in TLB.
184	*/	190	*/
185	if (index.p) {	191	if (index.p) {
186	printf("TLB entry not found.\n");	192	printf("TLB entry not found.\n");
187	goto fail;	193	goto fail;
188	}	194	}
189		195
190	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	196	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
191	if (!pte) {	197	if (!pte) {
192	switch (pfrc) {	198	switch (pfrc) {
193	case AS_PF_FAULT:	199	case AS_PF_FAULT:
194	goto fail;	200	goto fail;
195	break;	201	break;
196	case AS_PF_DEFER:	202	case AS_PF_DEFER:
197	/*	203	/*
198	* The page fault came during copy_from_uspace()	204	* The page fault came during copy_from_uspace()
199	* or copy_to_uspace().	205	* or copy_to_uspace().
200	*/	206	*/
201	page_table_unlock(AS, true);	207	page_table_unlock(AS, true);
202	return;	208	return;
203	default:	209	default:
204	panic("unexpected pfrc (%d)\n", pfrc);	210	panic("unexpected pfrc (%d)\n", pfrc);
205	}	211	}
206	}	212	}
207		213
208	/*	214	/*
209	* Read the faulting TLB entry.	215	* Read the faulting TLB entry.
210	*/	216	*/
211	tlbr();	217	tlbr();
212		218
213	/*	219	/*
214	* Record access to PTE.	220	* Record access to PTE.
215	*/	221	*/
216	pte->a = 1;	222	pte->a = 1;
217		223
218	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	224	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
219		225
220	/*	226	/*
221	* The entry is to be updated in TLB.	227	* The entry is to be updated in TLB.
222	*/	228	*/
223	if ((badvaddr/PAGE_SIZE) % 2 == 0)	229	if ((badvaddr/PAGE_SIZE) % 2 == 0)
224	cp0_entry_lo0_write(lo.value);	230	cp0_entry_lo0_write(lo.value);
225	else	231	else
226	cp0_entry_lo1_write(lo.value);	232	cp0_entry_lo1_write(lo.value);
227	cp0_pagemask_write(TLB_PAGE_MASK_16K);	233	cp0_pagemask_write(TLB_PAGE_MASK_16K);
228	tlbwi();	234	tlbwi();
229		235
230	page_table_unlock(AS, true);	236	page_table_unlock(AS, true);
231	return;	237	return;
232		238
233	fail:	239	fail:
234	page_table_unlock(AS, true);	240	page_table_unlock(AS, true);
235	tlb_invalid_fail(istate);	241	tlb_invalid_fail(istate);
236	}	242	}
237		243
238	/** Process TLB Modified Exception	244	/** Process TLB Modified Exception
239	*	245	*
240	* Process TLB Modified Exception.	246	* Process TLB Modified Exception.
241	*	247	*
242	* @param istate Interrupted register context.	248	* @param istate Interrupted register context.
243	*/	249	*/
244	void tlb_modified(istate_t *istate)	250	void tlb_modified(istate_t *istate)
245	{	251	{
246	tlb_index_t index;	252	tlb_index_t index;
247	__address badvaddr;	253	__address badvaddr;
248	entry_lo_t lo;	254	entry_lo_t lo;
249	entry_hi_t hi;	255	entry_hi_t hi;
250	pte_t *pte;	256	pte_t *pte;
251	int pfrc;	257	int pfrc;
252		258
253	badvaddr = cp0_badvaddr_read();	259	badvaddr = cp0_badvaddr_read();
254		260
255	/*	261	/*
256	* Locate the faulting entry in TLB.	262	* Locate the faulting entry in TLB.
257	*/	263	*/
258	hi.value = cp0_entry_hi_read();	264	hi.value = cp0_entry_hi_read();
259	prepare_entry_hi(&hi, hi.asid, badvaddr);	265	prepare_entry_hi(&hi, hi.asid, badvaddr);
260	cp0_entry_hi_write(hi.value);	266	cp0_entry_hi_write(hi.value);
261	tlbp();	267	tlbp();
262	index.value = cp0_index_read();	268	index.value = cp0_index_read();
263		269
264	page_table_lock(AS, true);	270	page_table_lock(AS, true);
265		271
266	/*	272	/*
267	* Fail if the entry is not in TLB.	273	* Fail if the entry is not in TLB.
268	*/	274	*/
269	if (index.p) {	275	if (index.p) {
270	printf("TLB entry not found.\n");	276	printf("TLB entry not found.\n");
271	goto fail;	277	goto fail;
272	}	278	}
273		279
274	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);	280	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
275	if (!pte) {	281	if (!pte) {
276	switch (pfrc) {	282	switch (pfrc) {
277	case AS_PF_FAULT:	283	case AS_PF_FAULT:
278	goto fail;	284	goto fail;
279	break;	285	break;
280	case AS_PF_DEFER:	286	case AS_PF_DEFER:
281	/*	287	/*
282	* The page fault came during copy_from_uspace()	288	* The page fault came during copy_from_uspace()
283	* or copy_to_uspace().	289	* or copy_to_uspace().
284	*/	290	*/
285	page_table_unlock(AS, true);	291	page_table_unlock(AS, true);
286	return;	292	return;
287	default:	293	default:
288	panic("unexpected pfrc (%d)\n", pfrc);	294	panic("unexpected pfrc (%d)\n", pfrc);
289	}	295	}
290	}	296	}
291		297
292	/*	298	/*
293	* Fail if the page is not writable.	299	* Fail if the page is not writable.
294	*/	300	*/
295	if (!pte->w)	301	if (!pte->w)
296	goto fail;	302	goto fail;
297		303
298	/*	304	/*
299	* Read the faulting TLB entry.	305	* Read the faulting TLB entry.
300	*/	306	*/
301	tlbr();	307	tlbr();
302		308
303	/*	309	/*
304	* Record access and write to PTE.	310	* Record access and write to PTE.
305	*/	311	*/
306	pte->a = 1;	312	pte->a = 1;
307	pte->d = 1;	313	pte->d = 1;
308		314
309	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);	315	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
310		316
311	/*	317	/*
312	* The entry is to be updated in TLB.	318	* The entry is to be updated in TLB.
313	*/	319	*/
314	if ((badvaddr/PAGE_SIZE) % 2 == 0)	320	if ((badvaddr/PAGE_SIZE) % 2 == 0)
315	cp0_entry_lo0_write(lo.value);	321	cp0_entry_lo0_write(lo.value);
316	else	322	else
317	cp0_entry_lo1_write(lo.value);	323	cp0_entry_lo1_write(lo.value);
318	cp0_pagemask_write(TLB_PAGE_MASK_16K);	324	cp0_pagemask_write(TLB_PAGE_MASK_16K);
319	tlbwi();	325	tlbwi();
320		326
321	page_table_unlock(AS, true);	327	page_table_unlock(AS, true);
322	return;	328	return;
323		329
324	fail:	330	fail:
325	page_table_unlock(AS, true);	331	page_table_unlock(AS, true);
326	tlb_modified_fail(istate);	332	tlb_modified_fail(istate);
327	}	333	}
328		334
329	void tlb_refill_fail(istate_t *istate)	335	void tlb_refill_fail(istate_t *istate)
330	{	336	{
331	char *symbol = "";	337	char *symbol = "";
332	char *sym2 = "";	338	char *sym2 = "";
333		339
334	char *s = get_symtab_entry(istate->epc);	340	char *s = get_symtab_entry(istate->epc);
335	if (s)	341	if (s)
336	symbol = s;	342	symbol = s;
337	s = get_symtab_entry(istate->ra);	343	s = get_symtab_entry(istate->ra);
338	if (s)	344	if (s)
339	sym2 = s;	345	sym2 = s;
340		346
341	fault_if_from_uspace(istate, "TLB Refill Exception on %P", cp0_badvaddr_read());	347	fault_if_from_uspace(istate, "TLB Refill Exception on %P", cp0_badvaddr_read());
342	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);	348	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
343	}	349	}
344		350
345		351
346	void tlb_invalid_fail(istate_t *istate)	352	void tlb_invalid_fail(istate_t *istate)
347	{	353	{
348	char *symbol = "";	354	char *symbol = "";
349		355
350	char *s = get_symtab_entry(istate->epc);	356	char *s = get_symtab_entry(istate->epc);
351	if (s)	357	if (s)
352	symbol = s;	358	symbol = s;
353	fault_if_from_uspace(istate, "TLB Invalid Exception on %P", cp0_badvaddr_read());	359	fault_if_from_uspace(istate, "TLB Invalid Exception on %P", cp0_badvaddr_read());
354	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	360	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
355	}	361	}
356		362
357	void tlb_modified_fail(istate_t *istate)	363	void tlb_modified_fail(istate_t *istate)
358	{	364	{
359	char *symbol = "";	365	char *symbol = "";
360		366
361	char *s = get_symtab_entry(istate->epc);	367	char *s = get_symtab_entry(istate->epc);
362	if (s)	368	if (s)
363	symbol = s;	369	symbol = s;
364	fault_if_from_uspace(istate, "TLB Modified Exception on %P", cp0_badvaddr_read());	370	fault_if_from_uspace(istate, "TLB Modified Exception on %P", cp0_badvaddr_read());
365	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	371	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
366	}	372	}
367		373
368	/** Try to find PTE for faulting address	374	/** Try to find PTE for faulting address
369	*	375	*
370	* Try to find PTE for faulting address.	376	* Try to find PTE for faulting address.
371	* The AS->lock must be held on entry to this function.	377	* The AS->lock must be held on entry to this function.
372	*	378	*
373	* @param badvaddr Faulting virtual address.	379	* @param badvaddr Faulting virtual address.
374	* @param access Access mode that caused the fault.	380	* @param access Access mode that caused the fault.
375	* @param istate Pointer to interrupted state.	381	* @param istate Pointer to interrupted state.
376	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
377	*	383	*
378	* @return PTE on success, NULL otherwise.	384	* @return PTE on success, NULL otherwise.
379	*/	385	*/
380	pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc)	386	pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc)
381	{	387	{
382	entry_hi_t hi;	388	entry_hi_t hi;
383	pte_t *pte;	389	pte_t *pte;
384		390
385	hi.value = cp0_entry_hi_read();	391	hi.value = cp0_entry_hi_read();
386		392
387	/*	393	/*
388	* Handler cannot succeed if the ASIDs don't match.	394	* Handler cannot succeed if the ASIDs don't match.
389	*/	395	*/
390	if (hi.asid != AS->asid) {	396	if (hi.asid != AS->asid) {
391	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	397	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
392	return NULL;	398	return NULL;
393	}	399	}
394		400
395	/*	401	/*
396	* Check if the mapping exists in page tables.	402	* Check if the mapping exists in page tables.
397	*/	403	*/
398	pte = page_mapping_find(AS, badvaddr);	404	pte = page_mapping_find(AS, badvaddr);
399	if (pte && pte->p) {	405	if (pte && pte->p) {
400	/*	406	/*
401	* Mapping found in page tables.	407	* Mapping found in page tables.
402	* Immediately succeed.	408	* Immediately succeed.
403	*/	409	*/
404	return pte;	410	return pte;
405	} else {	411	} else {
406	int rc;	412	int rc;
407		413
408	/*	414	/*
409	* Mapping not found in page tables.	415	* Mapping not found in page tables.
410	* Resort to higher-level page fault handler.	416	* Resort to higher-level page fault handler.
411	*/	417	*/
412	page_table_unlock(AS, true);	418	page_table_unlock(AS, true);
413	switch (rc = as_page_fault(badvaddr, access, istate)) {	419	switch (rc = as_page_fault(badvaddr, access, istate)) {
414	case AS_PF_OK:	420	case AS_PF_OK:
415	/*	421	/*
416	* The higher-level page fault handler succeeded,	422	* The higher-level page fault handler succeeded,
417	* The mapping ought to be in place.	423	* The mapping ought to be in place.
418	*/	424	*/
419	page_table_lock(AS, true);	425	page_table_lock(AS, true);
420	pte = page_mapping_find(AS, badvaddr);	426	pte = page_mapping_find(AS, badvaddr);
421	ASSERT(pte && pte->p);	427	ASSERT(pte && pte->p);
422	return pte;	428	return pte;
423	break;	429	break;
424	case AS_PF_DEFER:	430	case AS_PF_DEFER:
425	page_table_lock(AS, true);	431	page_table_lock(AS, true);
426	*pfrc = AS_PF_DEFER;	432	*pfrc = AS_PF_DEFER;
427	return NULL;	433	return NULL;
428	break;	434	break;
429	case AS_PF_FAULT:	435	case AS_PF_FAULT:
430	page_table_lock(AS, true);	436	page_table_lock(AS, true);
431	printf("Page fault.\n");	437	printf("Page fault.\n");
432	*pfrc = AS_PF_FAULT;	438	*pfrc = AS_PF_FAULT;
433	return NULL;	439	return NULL;
434	break;	440	break;
435	default:	441	default:
436	panic("unexpected rc (%d)\n", rc);	442	panic("unexpected rc (%d)\n", rc);
437	}	443	}
438		444
439	}	445	}
440	}	446	}
441		447
442	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)	448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
443	{	449	{
444	lo->value = 0;	450	lo->value = 0;
445	lo->g = g;	451	lo->g = g;
446	lo->v = v;	452	lo->v = v;
447	lo->d = d;	453	lo->d = d;
448	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
449	lo->pfn = pfn;	455	lo->pfn = pfn;
450	}	456	}
451		457
452	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
453	{	459	{
454	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
455	hi->asid = asid;	461	hi->asid = asid;
456	}	462	}
457		463
458	/** Print contents of TLB. */	464	/** Print contents of TLB. */
459	void tlb_print(void)	465	void tlb_print(void)
460	{	466	{
461	page_mask_t mask;	467	page_mask_t mask;
462	entry_lo_t lo0, lo1;	468	entry_lo_t lo0, lo1;
463	entry_hi_t hi, hi_save;	469	entry_hi_t hi, hi_save;
464	int i;	470	int i;
465		471
466	hi_save.value = cp0_entry_hi_read();	472	hi_save.value = cp0_entry_hi_read();
467		473
468	printf("TLB:\n");	474	printf("TLB:\n");
469	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	475	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
470	cp0_index_write(i);	476	cp0_index_write(i);
471	tlbr();	477	tlbr();
472		478
473	mask.value = cp0_pagemask_read();	479	mask.value = cp0_pagemask_read();
474	hi.value = cp0_entry_hi_read();	480	hi.value = cp0_entry_hi_read();
475	lo0.value = cp0_entry_lo0_read();	481	lo0.value = cp0_entry_lo0_read();
476	lo1.value = cp0_entry_lo1_read();	482	lo1.value = cp0_entry_lo1_read();
477		483
478	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"	484	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
479	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",	485	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
480	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,	486	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
481	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	487	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
482	}	488	}
483		489
484	cp0_entry_hi_write(hi_save.value);	490	cp0_entry_hi_write(hi_save.value);
485	}	491	}
486		492
487	/** Invalidate all not wired TLB entries. */	493	/** Invalidate all not wired TLB entries. */
488	void tlb_invalidate_all(void)	494	void tlb_invalidate_all(void)
489	{	495	{
490	ipl_t ipl;	496	ipl_t ipl;
491	entry_lo_t lo0, lo1;	497	entry_lo_t lo0, lo1;
492	entry_hi_t hi_save;	498	entry_hi_t hi_save;
493	int i;	499	int i;
494		500

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(root)/kernel/trunk/arch/mips32/src/mm/tlb.c – Rev 1595 → 1702