WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/interrupt.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup mips32interrupt
 * @{
 */
/** @file
 */
 
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <arch/cp0.h>
#include <time/clock.h>
#include <arch/drivers/arc.h>
 
#include <ipc/sysipc.h>
 
/** Disable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_disable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Enable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_enable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl | cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Restore interrupt priority level.
 *
 * @param ipl Saved interrupt priority level.
 */
void interrupts_restore(ipl_t ipl)
{
    cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
}
 
/** Read interrupt priority level.
 *
 * @return Current interrupt priority level.
 */
ipl_t interrupts_read(void)
{
    return cp0_status_read();
}
 
/* TODO: This is SMP unsafe!!! */
static unsigned long nextcount;
/** Start hardware clock */
static void timer_start(void)
{
    nextcount = cp0_compare_value + cp0_count_read();
    cp0_compare_write(nextcount);
}
 
static void timer_exception(int n, istate_t *istate)
{
    unsigned long drift;
 
    drift = cp0_count_read() - nextcount;
    while (drift > cp0_compare_value) {
        drift -= cp0_compare_value;
        CPU->missed_clock_ticks++;
    }
    nextcount = cp0_count_read() + cp0_compare_value - drift;
    cp0_compare_write(nextcount);
    clock();
}
 
static void swint0(int n, istate_t *istate)
{
    cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
    ipc_irq_send_notif(0);
}
 
static void swint1(int n, istate_t *istate)
{
    cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
    ipc_irq_send_notif(1);
}
 
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
    int_register(TIMER_IRQ, "timer", timer_exception);
    int_register(0, "swint0", swint0);
    int_register(1, "swint1", swint1);
    timer_start();
}
 
static void ipc_int(int n, istate_t *istate)
{
    ipc_irq_send_notif(n-INT_OFFSET);
}
 
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(unative_t irq)
{
    /* Do not allow to redefine timer */
    /* Swint0, Swint1 are already handled */
    if (irq == TIMER_IRQ || irq < 2)
        return;
    int_register(irq, "ipc_int", ipc_int);
}
 
 /** @}
 */
 
 

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/interrupt.c – Rev 1705 → 1780

Rev 1705		Rev 1780
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32interrupt	29	/** @addtogroup mips32interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <interrupt.h>	35	#include <interrupt.h>
36	#include <arch/interrupt.h>	36	#include <arch/interrupt.h>
37	#include <arch/types.h>	37	#include <arch/types.h>
38	#include <arch.h>	38	#include <arch.h>
39	#include <arch/cp0.h>	39	#include <arch/cp0.h>
40	#include <time/clock.h>	40	#include <time/clock.h>
41	#include <arch/drivers/arc.h>	41	#include <arch/drivers/arc.h>
42		42
43	#include <ipc/sysipc.h>	43	#include <ipc/sysipc.h>
44		44
45	/** Disable interrupts.	45	/** Disable interrupts.
46	*	46	*
47	* @return Old interrupt priority level.	47	* @return Old interrupt priority level.
48	*/	48	*/
49	ipl_t interrupts_disable(void)	49	ipl_t interrupts_disable(void)
50	{	50	{
51	ipl_t ipl = (ipl_t) cp0_status_read();	51	ipl_t ipl = (ipl_t) cp0_status_read();
52	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);	52	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
53	return ipl;	53	return ipl;
54	}	54	}
55		55
56	/** Enable interrupts.	56	/** Enable interrupts.
57	*	57	*
58	* @return Old interrupt priority level.	58	* @return Old interrupt priority level.
59	*/	59	*/
60	ipl_t interrupts_enable(void)	60	ipl_t interrupts_enable(void)
61	{	61	{
62	ipl_t ipl = (ipl_t) cp0_status_read();	62	ipl_t ipl = (ipl_t) cp0_status_read();
63	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);	63	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);
64	return ipl;	64	return ipl;
65	}	65	}
66		66
67	/** Restore interrupt priority level.	67	/** Restore interrupt priority level.
68	*	68	*
69	* @param ipl Saved interrupt priority level.	69	* @param ipl Saved interrupt priority level.
70	*/	70	*/
71	void interrupts_restore(ipl_t ipl)	71	void interrupts_restore(ipl_t ipl)
72	{	72	{
73	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));	73	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));
74	}	74	}
75		75
76	/** Read interrupt priority level.	76	/** Read interrupt priority level.
77	*	77	*
78	* @return Current interrupt priority level.	78	* @return Current interrupt priority level.
79	*/	79	*/
80	ipl_t interrupts_read(void)	80	ipl_t interrupts_read(void)
81	{	81	{
82	return cp0_status_read();	82	return cp0_status_read();
83	}	83	}
84		84
85	/* TODO: This is SMP unsafe!!! */	85	/* TODO: This is SMP unsafe!!! */
86	static unsigned long nextcount;	86	static unsigned long nextcount;
87	/** Start hardware clock */	87	/** Start hardware clock */
88	static void timer_start(void)	88	static void timer_start(void)
89	{	89	{
90	nextcount = cp0_compare_value + cp0_count_read();	90	nextcount = cp0_compare_value + cp0_count_read();
91	cp0_compare_write(nextcount);	91	cp0_compare_write(nextcount);
92	}	92	}
93		93
94	static void timer_exception(int n, istate_t *istate)	94	static void timer_exception(int n, istate_t *istate)
95	{	95	{
96	unsigned long drift;	96	unsigned long drift;
97		97
98	drift = cp0_count_read() - nextcount;	98	drift = cp0_count_read() - nextcount;
99	while (drift > cp0_compare_value) {	99	while (drift > cp0_compare_value) {
100	drift -= cp0_compare_value;	100	drift -= cp0_compare_value;
101	CPU->missed_clock_ticks++;	101	CPU->missed_clock_ticks++;
102	}	102	}
103	nextcount = cp0_count_read() + cp0_compare_value - drift;	103	nextcount = cp0_count_read() + cp0_compare_value - drift;
104	cp0_compare_write(nextcount);	104	cp0_compare_write(nextcount);
105	clock();	105	clock();
106	}	106	}
107		107
108	static void swint0(int n, istate_t *istate)	108	static void swint0(int n, istate_t *istate)
109	{	109	{
110	cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */	110	cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
111	ipc_irq_send_notif(0);	111	ipc_irq_send_notif(0);
112	}	112	}
113		113
114	static void swint1(int n, istate_t *istate)	114	static void swint1(int n, istate_t *istate)
115	{	115	{
116	cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */	116	cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
117	ipc_irq_send_notif(1);	117	ipc_irq_send_notif(1);
118	}	118	}
119		119
120	/* Initialize basic tables for exception dispatching */	120	/* Initialize basic tables for exception dispatching */
121	void interrupt_init(void)	121	void interrupt_init(void)
122	{	122	{
123	int_register(TIMER_IRQ, "timer", timer_exception);	123	int_register(TIMER_IRQ, "timer", timer_exception);
124	int_register(0, "swint0", swint0);	124	int_register(0, "swint0", swint0);
125	int_register(1, "swint1", swint1);	125	int_register(1, "swint1", swint1);
126	timer_start();	126	timer_start();
127	}	127	}
128		128
129	static void ipc_int(int n, istate_t *istate)	129	static void ipc_int(int n, istate_t *istate)
130	{	130	{
131	ipc_irq_send_notif(n-INT_OFFSET);	131	ipc_irq_send_notif(n-INT_OFFSET);
132	}	132	}
133		133
134	/* Reregister irq to be IPC-ready */	134	/* Reregister irq to be IPC-ready */
135	void irq_ipc_bind_arch(__native irq)	135	void irq_ipc_bind_arch(unative_t irq)
136	{	136	{
137	/* Do not allow to redefine timer */	137	/* Do not allow to redefine timer */
138	/* Swint0, Swint1 are already handled */	138	/* Swint0, Swint1 are already handled */
139	if (irq == TIMER_IRQ \|\| irq < 2)	139	if (irq == TIMER_IRQ \|\| irq < 2)
140	return;	140	return;
141	int_register(irq, "ipc_int", ipc_int);	141	int_register(irq, "ipc_int", ipc_int);
142	}	142	}
143		143
144	/** @}	144	/** @}
145	*/	145	*/
146		146
147		147