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Rev 1293 Rev 1615
1 
#
 1 
#
2 
# Copyright (C) 2003-2004 Jakub Jermar
 2 
# Copyright (C) 2003-2004 Jakub Jermar
3 
# All rights reserved.
 3 
# All rights reserved.
4 
#
 4 
#
5 
# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
6 
# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
7 
# are met:
 7 
# are met:
8 
#
 8 
#
9 
# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
10 
#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
11 
# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
12 
#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
13 
#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
14 
# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
16 
#
 16 
#
17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 
#
 27 
#
28 
 
 28 
 
29 
#include <arch/asm/regname.h>
 29 
#include <arch/asm/regname.h>
30
30
31 
.text
 31 
.text
32 
 
 32 
 
33 
.macro cp0_read reg
 33 
.macro cp0_read reg
34 
	mfc0 $2,\reg
 34 
	mfc0 $2,\reg
35 
	j $31
 35 
	j $31
36 
	nop
 36 
	nop
37 
.endm
 37 
.endm
38 
 
 38 
 
39 
.macro cp0_write reg
 39 
.macro cp0_write reg
40 
	mtc0 $4,\reg
 40 
	mtc0 $4,\reg
41 
	j $31
 41 
	j $31
42 
	nop
 42 
	nop
43 
.endm
 43 
.endm
44 
 
 44 
 
45 
.set noat
 45 
.set noat
46 
.set noreorder
 46 
.set noreorder
47 
.set nomacro
 47 
.set nomacro
48 
 
 48 
 
49 
.global cpu_halt
 49 
.global cpu_halt
50 
cpu_halt:
 50 
cpu_halt:
51 
	j cpu_halt
 51 
	j cpu_halt
52 
	nop
 52 
	nop
53 
 
 53 
 
54 
 
 54 
 
55 
.global memsetb
 55 
.global memsetb
56 
memsetb:
 56 
memsetb:
57 
	j _memsetb
 57 
	j _memsetb
58 
	nop
 58 
	nop
59 
 
 59 
 
60 
 
 60 
 
61 
.global memcpy
 61 
.global memcpy
62 
.global memcpy_from_uspace
 62 
.global memcpy_from_uspace
63 
.global memcpy_to_uspace
 63 
.global memcpy_to_uspace
64 
.global memcpy_from_uspace_failover_address
 64 
.global memcpy_from_uspace_failover_address
65 
.global memcpy_to_uspace_failover_address
 65 
.global memcpy_to_uspace_failover_address
66 
memcpy:
 66 
memcpy:
67 
memcpy_from_uspace:
 67 
memcpy_from_uspace:
68 
memcpy_to_uspace:
 68 
memcpy_to_uspace:
- 
 
 69 
	addiu	$v0,$a1,3
- 
 
 70 
	li	$v1,-4			# 0xfffffffffffffffc
- 
 
 71 
	and	$v0,$v0,$v1
- 
 
 72 
	beq	$a1,$v0,3f
- 
 
 73 
	move	$t0,$a0
- 
 
 74 
 
- 
 
 75 
0:
- 
 
 76 
	beq	$a2,$zero,2f
- 
 
 77 
	move	$a3,$zero
- 
 
 78 
 
- 
 
 79 
1:
- 
 
 80 
	addu	$v0,$a1,$a3
- 
 
 81 
	lbu	$a0,0($v0)
- 
 
 82 
	addu	$v1,$t0,$a3
- 
 
 83 
	addiu	$a3,$a3,1
- 
 
 84 
	bne	$a3,$a2,1b
- 
 
 85 
	sb	$a0,0($v1)
- 
 
 86 
 
- 
 
 87 
2:
- 
 
 88 
	jr	$ra
- 
 
 89 
	move	$v0,$a1
- 
 
 90 
 
- 
 
 91 
3:
- 
 
 92 
	addiu	$v0,$a0,3
- 
 
 93 
	and	$v0,$v0,$v1
- 
 
 94 
	bne	$a0,$v0,0b
69 
        srl     $t1,$a2,0x2
 95 
	srl	$t1,$a2,2
- 
 
 96 
 
70 
	beqz    $t1,1f
 97 
	beq	$t1,$zero,5f
71 
        move    $t0,$zero
 98 
	move	$a3,$zero
- 
 
 99 
 
72 
        move    $a3,$zero
 100 
	move	$a3,$zero
- 
 
 101 
	move	$a0,$zero
73 
2:
102 
4:
74 
        addu    $v0,$a1,$a3
 103 
	addu	$v0,$a1,$a0
75 
        lw      $v1,0($v0)
 104 
	lw	$v1,0($v0)
76 
        addiu   $t0,$t0,1
 105 
	addiu	$a3,$a3,1
77 
        addu    $v0,$a0,$a3
 106 
	addu	$v0,$t0,$a0
78 
        sw      $v1,0($v0)
 107 
	sw	$v1,0($v0)
79 
        bne     $t0,$t1,2b
 108 
	bne	$a3,$t1,4b
80 
        addiu   $a3,$a3,4
 109 
	addiu	$a0,$a0,4
- 
 
 110 
 
81 
1:
111 
5:
82 
        andi    $a2,$a2,0x3
 112 
	andi	$a2,$a2,0x3
83 
        beqz    $a2,3f
 113 
	beq	$a2,$zero,2b
84 
        move    $a3,$zero
 114 
	nop
- 
 
 115 
 
85 
        sll     $v0,$t0,0x2
 116 
	sll	$v0,$a3,2
86 
        addu    $t1,$a0,$v0
 117 
	addu	$t1,$v0,$t0
- 
 
 118 
	move	$a3,$zero
87 
        addu    $t0,$v0,$a1
 119 
	addu	$t0,$v0,$a1
88 
4:
120 
6:
89 
        addu    $v0,$t0,$a3
 121 
	addu	$v0,$t0,$a3
90 
        lbu     $a0,0($v0)
 122 
	lbu	$a0,0($v0)
91 
        addu    $v1,$t1,$a3
 123 
	addu	$v1,$t1,$a3
92 
        addiu   $a3,$a3,1
 124 
	addiu	$a3,$a3,1
93 
        bne     $a3,$a2,4b
 125 
	bne	$a3,$a2,6b
94 
        sb      $a0,0($v1)
 126 
	sb	$a0,0($v1)
95 
3:
127 
 
96 
        jr      $ra
 128 
	jr	$ra
97 
        move    $v0,$a1
 129 
	move	$v0,$a1
98 
 
 130 
 
99 
memcpy_from_uspace_failover_address:
 131 
memcpy_from_uspace_failover_address:
100 
memcpy_to_uspace_failover_address:
 132 
memcpy_to_uspace_failover_address:
101 
	jr	$ra
 133 
	jr	$ra
102 
	move	$v0, $zero
 134 
	move	$v0, $zero
103 
 
 135 
 
104 
 
 136 
 
105 
 
 137 
 
106 
.macro fpu_gp_save reg ctx
 138 
.macro fpu_gp_save reg ctx
107 
	mfc1 $t0,$\reg
 139 
	mfc1 $t0,$\reg
108 
	sw $t0, \reg*4(\ctx)
 140 
	sw $t0, \reg*4(\ctx)
109 
.endm
 141 
.endm
110 
 
 142 
 
111 
.macro fpu_gp_restore reg ctx
 143 
.macro fpu_gp_restore reg ctx
112 
	lw $t0, \reg*4(\ctx)
 144 
	lw $t0, \reg*4(\ctx)
113 
	mtc1 $t0,$\reg
 145 
	mtc1 $t0,$\reg
114 
.endm
 146 
.endm
115 
 
 147 
 
116 
.macro fpu_ct_save reg ctx
 148 
.macro fpu_ct_save reg ctx
117 
	cfc1 $t0,$1
 149 
	cfc1 $t0,$1
118 
	sw $t0, (\reg+32)*4(\ctx)
 150 
	sw $t0, (\reg+32)*4(\ctx)
119 
.endm
151 
.endm
120 
 
 152 
 
121 
.macro fpu_ct_restore reg ctx
 153 
.macro fpu_ct_restore reg ctx
122 
	lw $t0, (\reg+32)*4(\ctx)
 154 
	lw $t0, (\reg+32)*4(\ctx)
123 
	ctc1 $t0,$\reg
 155 
	ctc1 $t0,$\reg
124 
.endm
 156 
.endm
125 
 
 157 
 
126 
 
 158 
 
127 
.global fpu_context_save
 159 
.global fpu_context_save
128 
fpu_context_save:
 160 
fpu_context_save:
129 
#ifdef ARCH_HAS_FPU
 161 
#ifdef ARCH_HAS_FPU
130 
	fpu_gp_save 0,$a0
 162 
	fpu_gp_save 0,$a0
131 
	fpu_gp_save 1,$a0
 163 
	fpu_gp_save 1,$a0
132 
	fpu_gp_save 2,$a0
 164 
	fpu_gp_save 2,$a0
133 
	fpu_gp_save 3,$a0
 165 
	fpu_gp_save 3,$a0
134 
	fpu_gp_save 4,$a0
 166 
	fpu_gp_save 4,$a0
135 
	fpu_gp_save 5,$a0
 167 
	fpu_gp_save 5,$a0
136 
	fpu_gp_save 6,$a0
 168 
	fpu_gp_save 6,$a0
137 
	fpu_gp_save 7,$a0
 169 
	fpu_gp_save 7,$a0
138 
	fpu_gp_save 8,$a0
 170 
	fpu_gp_save 8,$a0
139 
	fpu_gp_save 9,$a0
 171 
	fpu_gp_save 9,$a0
140 
	fpu_gp_save 10,$a0
 172 
	fpu_gp_save 10,$a0
141 
	fpu_gp_save 11,$a0
 173 
	fpu_gp_save 11,$a0
142 
	fpu_gp_save 12,$a0
 174 
	fpu_gp_save 12,$a0
143 
	fpu_gp_save 13,$a0
 175 
	fpu_gp_save 13,$a0
144 
	fpu_gp_save 14,$a0
 176 
	fpu_gp_save 14,$a0
145 
	fpu_gp_save 15,$a0
 177 
	fpu_gp_save 15,$a0
146 
	fpu_gp_save 16,$a0
 178 
	fpu_gp_save 16,$a0
147 
	fpu_gp_save 17,$a0
 179 
	fpu_gp_save 17,$a0
148 
	fpu_gp_save 18,$a0
 180 
	fpu_gp_save 18,$a0
149 
	fpu_gp_save 19,$a0
 181 
	fpu_gp_save 19,$a0
150 
	fpu_gp_save 20,$a0
 182 
	fpu_gp_save 20,$a0
151 
	fpu_gp_save 21,$a0
 183 
	fpu_gp_save 21,$a0
152 
	fpu_gp_save 22,$a0
 184 
	fpu_gp_save 22,$a0
153 
	fpu_gp_save 23,$a0
 185 
	fpu_gp_save 23,$a0
154 
	fpu_gp_save 24,$a0
 186 
	fpu_gp_save 24,$a0
155 
	fpu_gp_save 25,$a0
 187 
	fpu_gp_save 25,$a0
156 
	fpu_gp_save 26,$a0
 188 
	fpu_gp_save 26,$a0
157 
	fpu_gp_save 27,$a0
 189 
	fpu_gp_save 27,$a0
158 
	fpu_gp_save 28,$a0
 190 
	fpu_gp_save 28,$a0
159 
	fpu_gp_save 29,$a0
 191 
	fpu_gp_save 29,$a0
160 
	fpu_gp_save 30,$a0
 192 
	fpu_gp_save 30,$a0
161 
	fpu_gp_save 31,$a0
 193 
	fpu_gp_save 31,$a0
162 
 
 194 
 
163 
	fpu_ct_save 1,$a0
 195 
	fpu_ct_save 1,$a0
164 
	fpu_ct_save 2,$a0
 196 
	fpu_ct_save 2,$a0
165 
	fpu_ct_save 3,$a0
 197 
	fpu_ct_save 3,$a0
166 
	fpu_ct_save 4,$a0
 198 
	fpu_ct_save 4,$a0
167 
	fpu_ct_save 5,$a0
 199 
	fpu_ct_save 5,$a0
168 
	fpu_ct_save 6,$a0
 200 
	fpu_ct_save 6,$a0
169 
	fpu_ct_save 7,$a0
 201 
	fpu_ct_save 7,$a0
170 
	fpu_ct_save 8,$a0
 202 
	fpu_ct_save 8,$a0
171 
	fpu_ct_save 9,$a0
 203 
	fpu_ct_save 9,$a0
172 
	fpu_ct_save 10,$a0
 204 
	fpu_ct_save 10,$a0
173 
	fpu_ct_save 11,$a0
 205 
	fpu_ct_save 11,$a0
174 
	fpu_ct_save 12,$a0
 206 
	fpu_ct_save 12,$a0
175 
	fpu_ct_save 13,$a0
 207 
	fpu_ct_save 13,$a0
176 
	fpu_ct_save 14,$a0
 208 
	fpu_ct_save 14,$a0
177 
	fpu_ct_save 15,$a0
 209 
	fpu_ct_save 15,$a0
178 
	fpu_ct_save 16,$a0
 210 
	fpu_ct_save 16,$a0
179 
	fpu_ct_save 17,$a0
 211 
	fpu_ct_save 17,$a0
180 
	fpu_ct_save 18,$a0
 212 
	fpu_ct_save 18,$a0
181 
	fpu_ct_save 19,$a0
 213 
	fpu_ct_save 19,$a0
182 
	fpu_ct_save 20,$a0
 214 
	fpu_ct_save 20,$a0
183 
	fpu_ct_save 21,$a0
 215 
	fpu_ct_save 21,$a0
184 
	fpu_ct_save 22,$a0
 216 
	fpu_ct_save 22,$a0
185 
	fpu_ct_save 23,$a0
 217 
	fpu_ct_save 23,$a0
186 
	fpu_ct_save 24,$a0
 218 
	fpu_ct_save 24,$a0
187 
	fpu_ct_save 25,$a0
 219 
	fpu_ct_save 25,$a0
188 
	fpu_ct_save 26,$a0
 220 
	fpu_ct_save 26,$a0
189 
	fpu_ct_save 27,$a0
 221 
	fpu_ct_save 27,$a0
190 
	fpu_ct_save 28,$a0
 222 
	fpu_ct_save 28,$a0
191 
	fpu_ct_save 29,$a0
 223 
	fpu_ct_save 29,$a0
192 
	fpu_ct_save 30,$a0
 224 
	fpu_ct_save 30,$a0
193 
	fpu_ct_save 31,$a0
 225 
	fpu_ct_save 31,$a0
194 
#endif
226 
#endif
195 
	j $ra
 227 
	j $ra
196 
	nop
 228 
	nop
197 
 
 229 
 
198 
.global fpu_context_restore
 230 
.global fpu_context_restore
199 
fpu_context_restore:
 231 
fpu_context_restore:
200 
#ifdef ARCH_HAS_FPU
 232 
#ifdef ARCH_HAS_FPU
201 
	fpu_gp_restore 0,$a0
 233 
	fpu_gp_restore 0,$a0
202 
	fpu_gp_restore 1,$a0
 234 
	fpu_gp_restore 1,$a0
203 
	fpu_gp_restore 2,$a0
 235 
	fpu_gp_restore 2,$a0
204 
	fpu_gp_restore 3,$a0
 236 
	fpu_gp_restore 3,$a0
205 
	fpu_gp_restore 4,$a0
 237 
	fpu_gp_restore 4,$a0
206 
	fpu_gp_restore 5,$a0
 238 
	fpu_gp_restore 5,$a0
207 
	fpu_gp_restore 6,$a0
 239 
	fpu_gp_restore 6,$a0
208 
	fpu_gp_restore 7,$a0
 240 
	fpu_gp_restore 7,$a0
209 
	fpu_gp_restore 8,$a0
 241 
	fpu_gp_restore 8,$a0
210 
	fpu_gp_restore 9,$a0
 242 
	fpu_gp_restore 9,$a0
211 
	fpu_gp_restore 10,$a0
 243 
	fpu_gp_restore 10,$a0
212 
	fpu_gp_restore 11,$a0
 244 
	fpu_gp_restore 11,$a0
213 
	fpu_gp_restore 12,$a0
 245 
	fpu_gp_restore 12,$a0
214 
	fpu_gp_restore 13,$a0
 246 
	fpu_gp_restore 13,$a0
215 
	fpu_gp_restore 14,$a0
 247 
	fpu_gp_restore 14,$a0
216 
	fpu_gp_restore 15,$a0
 248 
	fpu_gp_restore 15,$a0
217 
	fpu_gp_restore 16,$a0
 249 
	fpu_gp_restore 16,$a0
218 
	fpu_gp_restore 17,$a0
 250 
	fpu_gp_restore 17,$a0
219 
	fpu_gp_restore 18,$a0
 251 
	fpu_gp_restore 18,$a0
220 
	fpu_gp_restore 19,$a0
 252 
	fpu_gp_restore 19,$a0
221 
	fpu_gp_restore 20,$a0
 253 
	fpu_gp_restore 20,$a0
222 
	fpu_gp_restore 21,$a0
 254 
	fpu_gp_restore 21,$a0
223 
	fpu_gp_restore 22,$a0
 255 
	fpu_gp_restore 22,$a0
224 
	fpu_gp_restore 23,$a0
 256 
	fpu_gp_restore 23,$a0
225 
	fpu_gp_restore 24,$a0
 257 
	fpu_gp_restore 24,$a0
226 
	fpu_gp_restore 25,$a0
 258 
	fpu_gp_restore 25,$a0
227 
	fpu_gp_restore 26,$a0
 259 
	fpu_gp_restore 26,$a0
228 
	fpu_gp_restore 27,$a0
 260 
	fpu_gp_restore 27,$a0
229 
	fpu_gp_restore 28,$a0
 261 
	fpu_gp_restore 28,$a0
230 
	fpu_gp_restore 29,$a0
 262 
	fpu_gp_restore 29,$a0
231 
	fpu_gp_restore 30,$a0
 263 
	fpu_gp_restore 30,$a0
232 
	fpu_gp_restore 31,$a0
 264 
	fpu_gp_restore 31,$a0
233 
 
 265 
 
234 
	fpu_ct_restore 1,$a0
 266 
	fpu_ct_restore 1,$a0
235 
	fpu_ct_restore 2,$a0
 267 
	fpu_ct_restore 2,$a0
236 
	fpu_ct_restore 3,$a0
 268 
	fpu_ct_restore 3,$a0
237 
	fpu_ct_restore 4,$a0
 269 
	fpu_ct_restore 4,$a0
238 
	fpu_ct_restore 5,$a0
 270 
	fpu_ct_restore 5,$a0
239 
	fpu_ct_restore 6,$a0
 271 
	fpu_ct_restore 6,$a0
240 
	fpu_ct_restore 7,$a0
 272 
	fpu_ct_restore 7,$a0
241 
	fpu_ct_restore 8,$a0
 273 
	fpu_ct_restore 8,$a0
242 
	fpu_ct_restore 9,$a0
 274 
	fpu_ct_restore 9,$a0
243 
	fpu_ct_restore 10,$a0
 275 
	fpu_ct_restore 10,$a0
244 
	fpu_ct_restore 11,$a0
 276 
	fpu_ct_restore 11,$a0
245 
	fpu_ct_restore 12,$a0
 277 
	fpu_ct_restore 12,$a0
246 
	fpu_ct_restore 13,$a0
 278 
	fpu_ct_restore 13,$a0
247 
	fpu_ct_restore 14,$a0
 279 
	fpu_ct_restore 14,$a0
248 
	fpu_ct_restore 15,$a0
 280 
	fpu_ct_restore 15,$a0
249 
	fpu_ct_restore 16,$a0
 281 
	fpu_ct_restore 16,$a0
250 
	fpu_ct_restore 17,$a0
 282 
	fpu_ct_restore 17,$a0
251 
	fpu_ct_restore 18,$a0
 283 
	fpu_ct_restore 18,$a0
252 
	fpu_ct_restore 19,$a0
 284 
	fpu_ct_restore 19,$a0
253 
	fpu_ct_restore 20,$a0
 285 
	fpu_ct_restore 20,$a0
254 
	fpu_ct_restore 21,$a0
 286 
	fpu_ct_restore 21,$a0
255 
	fpu_ct_restore 22,$a0
 287 
	fpu_ct_restore 22,$a0
256 
	fpu_ct_restore 23,$a0
 288 
	fpu_ct_restore 23,$a0
257 
	fpu_ct_restore 24,$a0
 289 
	fpu_ct_restore 24,$a0
258 
	fpu_ct_restore 25,$a0
 290 
	fpu_ct_restore 25,$a0
259 
	fpu_ct_restore 26,$a0
 291 
	fpu_ct_restore 26,$a0
260 
	fpu_ct_restore 27,$a0
 292 
	fpu_ct_restore 27,$a0
261 
	fpu_ct_restore 28,$a0
 293 
	fpu_ct_restore 28,$a0
262 
	fpu_ct_restore 29,$a0
 294 
	fpu_ct_restore 29,$a0
263 
	fpu_ct_restore 30,$a0
 295 
	fpu_ct_restore 30,$a0
264 
	fpu_ct_restore 31,$a0
 296 
	fpu_ct_restore 31,$a0
265 
#endif
297 
#endif
266 
	j $ra
 298 
	j $ra
267 
	nop
 299 
	nop
268 
 
 300