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 */
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 */
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#ifndef __mips_TLB_H__
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#ifndef __mips_TLB_H__
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#define __mips_TLB_H__
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#define __mips_TLB_H__
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#define PAGE_UNCACHED           2
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#define PAGE_CACHEABLE_EXC_WRITE    5
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struct entry_lo {
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struct entry_lo {
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    unsigned g : 1;
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    unsigned g : 1;     /* global bit */
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    unsigned v : 1;
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    unsigned v : 1;     /* valid bit */
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    unsigned d : 1;
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    unsigned d : 1;     /* dirty/write-protect bit */
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    unsigned c : 3;
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    unsigned c : 3;     /* cache coherency attribute */
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    unsigned pfn : 24;
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    unsigned pfn : 24;  /* frame number */
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    unsigned : 2;
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    unsigned : 2;
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} __attribute__ ((packed));
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} __attribute__ ((packed));
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struct entry_hi {
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struct entry_hi {
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    unsigned asid : 8;
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    unsigned asid : 8;
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    struct entry_lo lo1;
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    struct entry_lo lo1;
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    struct entry_hi hi;
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    struct entry_hi hi;
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    struct page_mask mask;
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    struct page_mask mask;
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} __attribute__ ((packed));
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} __attribute__ ((packed));
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typedef struct entry_lo pte_t;
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extern void tlb_refill(void);
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extern void tlb_refill(void);
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extern void tlb_invalid(void);
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extern void tlb_invalid(void);
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#endif
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#endif