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#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
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#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
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#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
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#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
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#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
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#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
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#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
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#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
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  { \
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  { \
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      __u32 retval; \
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      uint32_t retval; \
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      asm("mfc0 %0, $" #reg : "=r"(retval)); \
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      asm("mfc0 %0, $" #reg : "=r"(retval)); \
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      return retval; \
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      return retval; \
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  }
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  }
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#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
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#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
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 { \
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 { \
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    asm("mtc0 %0, $" #reg : : "r"(val) ); \
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    asm("mtc0 %0, $" #reg : : "r"(val) ); \
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 }
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 }
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GEN_READ_CP0(index, 0);
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GEN_READ_CP0(index, 0);