WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/include/cp0.h


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup mips32cpu
 * @{
 */
/** @file
 */
 
#ifndef __mips32_CP0_H__
#define __mips32_CP0_H__
 
#include <arch/types.h>
#include <arch/mm/tlb.h>
 
#define cp0_status_ie_enabled_bit   (1<<0)
#define cp0_status_exl_exception_bit    (1<<1)
#define cp0_status_erl_error_bit    (1<<2)
#define cp0_status_um_bit           (1<<4)
#define cp0_status_bev_bootstrap_bit    (1<<22)
#define cp0_status_fpu_bit              (1<<29)
 
#define cp0_status_im_shift     8
#define cp0_status_im_mask              0xff00
 
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
 
#define fpu_cop_id 1
 
/*
 * Magic value for use in msim.
 */
#define cp0_compare_value       100000
 
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
  { \
      __u32 retval; \
      asm("mfc0 %0, $" #reg : "=r"(retval)); \
      return retval; \
  }
 
#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
 { \
    asm("mtc0 %0, $" #reg : : "r"(val) ); \
 }
 
GEN_READ_CP0(index, 0);
GEN_WRITE_CP0(index, 0);
 
GEN_READ_CP0(random, 1);
 
GEN_READ_CP0(entry_lo0, 2);
GEN_WRITE_CP0(entry_lo0, 2);
 
GEN_READ_CP0(entry_lo1, 3);
GEN_WRITE_CP0(entry_lo1, 3);
 
GEN_READ_CP0(context, 4);
GEN_WRITE_CP0(context, 4);
 
GEN_READ_CP0(pagemask, 5);
GEN_WRITE_CP0(pagemask, 5);
 
GEN_READ_CP0(wired, 6);
GEN_WRITE_CP0(wired, 6);
 
GEN_READ_CP0(badvaddr, 8);
 
GEN_READ_CP0(count, 9);
GEN_WRITE_CP0(count, 9);
 
GEN_READ_CP0(entry_hi, 10);
GEN_WRITE_CP0(entry_hi, 10);
 
GEN_READ_CP0(compare, 11);
GEN_WRITE_CP0(compare, 11);
 
GEN_READ_CP0(status, 12);
GEN_WRITE_CP0(status, 12);
 
GEN_READ_CP0(cause, 13);
GEN_WRITE_CP0(cause, 13);
 
GEN_READ_CP0(epc, 14);
GEN_WRITE_CP0(epc, 14);
 
GEN_READ_CP0(prid, 15);
 
#endif
 
 /** @}
 */
 
 

Rev 1434	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup mips32cpu
-		30	* @{
-		31	*/
-		32	/** @file
-		33	*/
-		34
29	#ifndef __mips32_CP0_H__	35	#ifndef __mips32_CP0_H__
30	#define __mips32_CP0_H__	36	#define __mips32_CP0_H__
31		37
32	#include <arch/types.h>	38	#include <arch/types.h>
33	#include <arch/mm/tlb.h>	39	#include <arch/mm/tlb.h>
34		40
35	#define cp0_status_ie_enabled_bit (1<<0)	41	#define cp0_status_ie_enabled_bit (1<<0)
36	#define cp0_status_exl_exception_bit (1<<1)	42	#define cp0_status_exl_exception_bit (1<<1)
37	#define cp0_status_erl_error_bit (1<<2)	43	#define cp0_status_erl_error_bit (1<<2)
38	#define cp0_status_um_bit (1<<4)	44	#define cp0_status_um_bit (1<<4)
39	#define cp0_status_bev_bootstrap_bit (1<<22)	45	#define cp0_status_bev_bootstrap_bit (1<<22)
40	#define cp0_status_fpu_bit (1<<29)	46	#define cp0_status_fpu_bit (1<<29)
41		47
42	#define cp0_status_im_shift 8	48	#define cp0_status_im_shift 8
43	#define cp0_status_im_mask 0xff00	49	#define cp0_status_im_mask 0xff00
44		50
45	#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)	51	#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
46	#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)	52	#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
47		53
48	#define fpu_cop_id 1	54	#define fpu_cop_id 1
49		55
50	/*	56	/*
51	* Magic value for use in msim.	57	* Magic value for use in msim.
52	*/	58	*/
53	#define cp0_compare_value 100000	59	#define cp0_compare_value 100000
54		60
55	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))	61	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
56	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)	62	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)
57	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))	63	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
58	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))	64	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))
59		65
60	#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \	66	#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
61	{ \	67	{ \
62	__u32 retval; \	68	__u32 retval; \
63	asm("mfc0 %0, $" #reg : "=r"(retval)); \	69	asm("mfc0 %0, $" #reg : "=r"(retval)); \
64	return retval; \	70	return retval; \
65	}	71	}
66		72
67	#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \	73	#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
68	{ \	74	{ \
69	asm("mtc0 %0, $" #reg : : "r"(val) ); \	75	asm("mtc0 %0, $" #reg : : "r"(val) ); \
70	}	76	}
71		77
72	GEN_READ_CP0(index, 0);	78	GEN_READ_CP0(index, 0);
73	GEN_WRITE_CP0(index, 0);	79	GEN_WRITE_CP0(index, 0);
74		80
75	GEN_READ_CP0(random, 1);	81	GEN_READ_CP0(random, 1);
76		82
77	GEN_READ_CP0(entry_lo0, 2);	83	GEN_READ_CP0(entry_lo0, 2);
78	GEN_WRITE_CP0(entry_lo0, 2);	84	GEN_WRITE_CP0(entry_lo0, 2);
79		85
80	GEN_READ_CP0(entry_lo1, 3);	86	GEN_READ_CP0(entry_lo1, 3);
81	GEN_WRITE_CP0(entry_lo1, 3);	87	GEN_WRITE_CP0(entry_lo1, 3);
82		88
83	GEN_READ_CP0(context, 4);	89	GEN_READ_CP0(context, 4);
84	GEN_WRITE_CP0(context, 4);	90	GEN_WRITE_CP0(context, 4);
85		91
86	GEN_READ_CP0(pagemask, 5);	92	GEN_READ_CP0(pagemask, 5);
87	GEN_WRITE_CP0(pagemask, 5);	93	GEN_WRITE_CP0(pagemask, 5);
88		94
89	GEN_READ_CP0(wired, 6);	95	GEN_READ_CP0(wired, 6);
90	GEN_WRITE_CP0(wired, 6);	96	GEN_WRITE_CP0(wired, 6);
91		97
92	GEN_READ_CP0(badvaddr, 8);	98	GEN_READ_CP0(badvaddr, 8);
93		99
94	GEN_READ_CP0(count, 9);	100	GEN_READ_CP0(count, 9);
95	GEN_WRITE_CP0(count, 9);	101	GEN_WRITE_CP0(count, 9);
96		102
97	GEN_READ_CP0(entry_hi, 10);	103	GEN_READ_CP0(entry_hi, 10);
98	GEN_WRITE_CP0(entry_hi, 10);	104	GEN_WRITE_CP0(entry_hi, 10);
99		105
100	GEN_READ_CP0(compare, 11);	106	GEN_READ_CP0(compare, 11);
101	GEN_WRITE_CP0(compare, 11);	107	GEN_WRITE_CP0(compare, 11);
102		108
103	GEN_READ_CP0(status, 12);	109	GEN_READ_CP0(status, 12);
104	GEN_WRITE_CP0(status, 12);	110	GEN_WRITE_CP0(status, 12);
105		111
106	GEN_READ_CP0(cause, 13);	112	GEN_READ_CP0(cause, 13);
107	GEN_WRITE_CP0(cause, 13);	113	GEN_WRITE_CP0(cause, 13);
108		114
109	GEN_READ_CP0(epc, 14);	115	GEN_READ_CP0(epc, 14);
110	GEN_WRITE_CP0(epc, 14);	116	GEN_WRITE_CP0(epc, 14);
111		117
112	GEN_READ_CP0(prid, 15);	118	GEN_READ_CP0(prid, 15);
113		119
114	#endif	120	#endif
-		121
-		122	/** @}
-		123	*/
-		124
115		125

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/include/cp0.h – Rev 1434 → 1702