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| Rev 1096 | Rev 1434 | ||
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| 47 | 47 | ||
| 48 | #define fpu_cop_id 1 |
48 | #define fpu_cop_id 1 |
| 49 | 49 | ||
| 50 | /* |
50 | /* |
| 51 | * Magic value for use in msim. |
51 | * Magic value for use in msim. |
| 52 | * On AMD Duron 800Mhz, this roughly seems like one us. |
- | |
| 53 | */ |
52 | */ |
| 54 | #define cp0_compare_value 10000 |
53 | #define cp0_compare_value 100000 |
| 55 | 54 | ||
| 56 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
55 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
| 57 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
56 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
| 58 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
57 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
| 59 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
58 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |