WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/mm/tlb.c



 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/barrier.h>
#include <arch/interrupt.h>
#include <typedefs.h>
#include <panic.h>
 
/** Invalidate all TLB entries. */
void tlb_invalidate_all(void)
{
    /* TODO */

        srlz_i();
    }
   
    __asm__ volatile (
        "mov r8=psr;;\n"
        "rsm %0;;\n"            /* PSR_IC_MASK */
 
        "srlz.d;;\n"
        "srlz.i;;\n"
        "mov cr.ifa=%1\n"       /* va */
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
        "(p6) itc.i %3;;\n"
        "(p7) itc.d %3;;\n"
        "mov psr.l=r8;;\n"
        "srlz.d;;\n"
        :
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
        : "p6", "p7", "r8"
    );
   
    if (restore_rr) {
        rr_write(VA_REGION(va),rr.word);
        srlz_d();

        srlz_i();
    }
 
    __asm__ volatile (
        "mov r8=psr;;\n"
        "rsm %0;;\n"            /* PSR_IC_MASK */
 
        "srlz.d;;\n"
        "srlz.i;;\n"
        "mov cr.ifa=%1\n"           /* va */         
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
        "cmp.eq p6,p7=%5,r0;;\n"    /* decide between itr and dtr */
        "(p6) itr.i itr[%4]=%3;;\n"
        "(p7) itr.d dtr[%4]=%3;;\n"
        "mov psr.l=r8;;\n"
        "srlz.d;;\n"
        :
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
        : "p6", "p7", "r8"
    );
   
    if (restore_rr) {
        rr_write(VA_REGION(va),rr.word);
        srlz_d();
        srlz_i();
    }
}
 
void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}
 
void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s: %P\n", __FUNCTION__, pstate->cr_ifa);
}
 
void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}
 
void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}
 
void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}
 
void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}
 
void page_not_present(__u64 vector, struct exception_regdump *pstate)
{
    panic("%s\n", __FUNCTION__);
}

Rev 899	Rev 900
Line 31...	Line 31...
31	*/	31	*/
32		32
33	#include <mm/tlb.h>	33	#include <mm/tlb.h>
34	#include <arch/mm/tlb.h>	34	#include <arch/mm/tlb.h>
35	#include <arch/barrier.h>	35	#include <arch/barrier.h>
-		36	#include <arch/interrupt.h>
36	#include <typedefs.h>	37	#include <typedefs.h>
-		38	#include <panic.h>
37		39
38	/** Invalidate all TLB entries. */	40	/** Invalidate all TLB entries. */
39	void tlb_invalidate_all(void)	41	void tlb_invalidate_all(void)
40	{	42	{
41	/* TODO */	43	/* TODO */
Line 100...	Line 102...
100	srlz_i();	102	srlz_i();
101	}	103	}
102		104
103	__asm__ volatile (	105	__asm__ volatile (
104	"mov r8=psr;;\n"	106	"mov r8=psr;;\n"
105	"and r9=r8,%0;;\n" /* (~PSR_IC_MASK) */	107	"rsm %0;;\n" /* PSR_IC_MASK */
106	"mov psr.l=r9;;\n"	-
107	"srlz.d;;\n"	108	"srlz.d;;\n"
108	"srlz.i;;\n"	109	"srlz.i;;\n"
109	"mov cr.ifa=%1\n" /* va */	110	"mov cr.ifa=%1\n" /* va */
110	"mov cr.itir=%2;;\n" /* entry.word[1] */	111	"mov cr.itir=%2;;\n" /* entry.word[1] */
111	"cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */	112	"cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */
112	"(p6) itc.i %3;;\n"	113	"(p6) itc.i %3;;\n"
113	"(p7) itc.d %3;;\n"	114	"(p7) itc.d %3;;\n"
114	"mov psr.l=r8;;\n"	115	"mov psr.l=r8;;\n"
115	"srlz.d;;\n"	116	"srlz.d;;\n"
116	:	117	:
117	: "r" (~PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)	118	: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
118	: "p6", "p7", "r8", "r9"	119	: "p6", "p7", "r8"
119	);	120	);
120		121
121	if (restore_rr) {	122	if (restore_rr) {
122	rr_write(VA_REGION(va),rr.word);	123	rr_write(VA_REGION(va),rr.word);
123	srlz_d();	124	srlz_d();
Line 180...	Line 181...
180	srlz_i();	181	srlz_i();
181	}	182	}
182		183
183	__asm__ volatile (	184	__asm__ volatile (
184	"mov r8=psr;;\n"	185	"mov r8=psr;;\n"
185	"and r9=r8,%0;;\n" /* (~PSR_IC_MASK) */	186	"rsm %0;;\n" /* PSR_IC_MASK */
186	"mov psr.l=r9;;\n"	-
187	"srlz.d;;\n"	187	"srlz.d;;\n"
188	"srlz.i;;\n"	188	"srlz.i;;\n"
189	"mov cr.ifa=%1\n" /* va */	189	"mov cr.ifa=%1\n" /* va */
190	"mov cr.itir=%2;;\n" /* entry.word[1] */	190	"mov cr.itir=%2;;\n" /* entry.word[1] */
191	"cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */	191	"cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */
192	"(p6) itr.i itr[%4]=%3;;\n"	192	"(p6) itr.i itr[%4]=%3;;\n"
193	"(p7) itr.d dtr[%4]=%3;;\n"	193	"(p7) itr.d dtr[%4]=%3;;\n"
194	"mov psr.l=r8;;\n"	194	"mov psr.l=r8;;\n"
195	"srlz.d;;\n"	195	"srlz.d;;\n"
196	:	196	:
197	:"r" (~PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)	197	: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
198	: "p6", "p7", "r8", "r9"	198	: "p6", "p7", "r8"
199	);	199	);
200		200
201	if (restore_rr) {	201	if (restore_rr) {
202	rr_write(VA_REGION(va),rr.word);	202	rr_write(VA_REGION(va),rr.word);
203	srlz_d();	203	srlz_d();
204	srlz_i();	204	srlz_i();
205	}	205	}
206	}	206	}
207		207
208	void alternate_instruction_tlb_fault(void)	208	void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate)
209	{	209	{
210	panic("%s\n", __FUNCTION__);	210	panic("%s\n", __FUNCTION__);
211	}	211	}
212		212
213	void alternate_data_tlb_fault(void)	213	void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate)
214	{	214	{
215	panic("%s\n", __FUNCTION__);	215	panic("%s: %P\n", __FUNCTION__, pstate->cr_ifa);
216	}	216	}
217		217
218	void data_nested_tlb_fault(void)	218	void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate)
219	{	219	{
220	panic("%s\n", __FUNCTION__);	220	panic("%s\n", __FUNCTION__);
221	}	221	}
222		222
223	void data_dirty_bit_fault(void)	223	void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate)
224	{	224	{
225	panic("%s\n", __FUNCTION__);	225	panic("%s\n", __FUNCTION__);
226	}	226	}
227		227
228	void instruction_access_bit_fault(void)	228	void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
229	{	229	{
230	panic("%s\n", __FUNCTION__);	230	panic("%s\n", __FUNCTION__);
231	}	231	}
232		232
233	void data_access_bit_fault(void)	233	void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
234	{	234	{
235	panic("%s\n", __FUNCTION__);	235	panic("%s\n", __FUNCTION__);
236	}	236	}
237		237
238	void page_not_present(void)	238	void page_not_present(__u64 vector, struct exception_regdump *pstate)
239	{	239	{
240	panic("%s\n", __FUNCTION__);	240	panic("%s\n", __FUNCTION__);
241	}	241	}

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/mm/tlb.c – Rev 899 → 900