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| Rev 1621 | Rev 1675 | ||
|---|---|---|---|
| Line 187... | Line 187... | ||
| 187 | srlz_d(); |
187 | srlz_d(); |
| 188 | srlz_i(); |
188 | srlz_i(); |
| 189 | } |
189 | } |
| 190 | } |
190 | } |
| 191 | 191 | ||
| 192 | - | ||
| 193 | /** Insert data into data translation cache. |
192 | /** Insert data into data translation cache. |
| 194 | * |
193 | * |
| 195 | * @param va Virtual page address. |
194 | * @param va Virtual page address. |
| 196 | * @param asid Address space identifier. |
195 | * @param asid Address space identifier. |
| 197 | * @param entry The rest of TLB entry as required by TLB insertion format. |
196 | * @param entry The rest of TLB entry as required by TLB insertion format. |
| Line 339... | Line 338... | ||
| 339 | } |
338 | } |
| 340 | } |
339 | } |
| 341 | 340 | ||
| 342 | /** Insert data into DTLB. |
341 | /** Insert data into DTLB. |
| 343 | * |
342 | * |
| 344 | * @param va Virtual page address. |
343 | * @param page Virtual page address including VRN bits. |
| 345 | * @param asid Address space identifier. |
344 | * @param frame Physical frame address. |
| 346 | * @param entry The rest of TLB entry as required by TLB insertion format. |
- | |
| 347 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
345 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
| 348 | * @param tr Translation register if dtr is true, ignored otherwise. |
346 | * @param tr Translation register if dtr is true, ignored otherwise. |
| 349 | */ |
347 | */ |
| 350 | void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr) |
348 | void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr) |
| 351 | { |
349 | { |
| Line 367... | Line 365... | ||
| 367 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr); |
365 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr); |
| 368 | else |
366 | else |
| 369 | dtc_mapping_insert(page, ASID_KERNEL, entry); |
367 | dtc_mapping_insert(page, ASID_KERNEL, entry); |
| 370 | } |
368 | } |
| 371 | 369 | ||
| - | 370 | /** Purge kernel entries from DTR. |
|
| - | 371 | * |
|
| - | 372 | * Purge DTR entries used by the kernel. |
|
| - | 373 | * |
|
| - | 374 | * @param page Virtual page address including VRN bits. |
|
| - | 375 | * @param width Width of the purge in bits. |
|
| - | 376 | */ |
|
| - | 377 | void dtr_purge(__address page, count_t width) |
|
| - | 378 | { |
|
| - | 379 | __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
|
| - | 380 | } |
|
| - | 381 | ||
| - | 382 | ||
| 372 | /** Copy content of PTE into data translation cache. |
383 | /** Copy content of PTE into data translation cache. |
| 373 | * |
384 | * |
| 374 | * @param t PTE. |
385 | * @param t PTE. |
| 375 | */ |
386 | */ |
| 376 | void dtc_pte_copy(pte_t *t) |
387 | void dtc_pte_copy(pte_t *t) |