WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/mm/tlb.c

  * @param istate Structure with saved interruption state.
  */
 void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
+{
     region_register rr;
+    rid_t rid;
     __address va;
     pte_t *t;
     va = istate->cr_ifa;    /* faulting address */
+    rr.word = rr_read(VA2VRN(va));
+    rid = rr.map.rid;
     page_table_lock(AS, true);
     t = page_mapping_find(AS, va);
     if (t) {
         /*
          * The mapping was found in software page hash table.
     } else {
         /*
          * Forward the page fault to address space page fault handler.
          */
         page_table_unlock(AS, true);
-        if (as_page_fault(va, istate) == AS_PF_FAULT) {
+        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, istate->cr_ifa, rr.map.rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+        }
+    }
+}
 /** Data TLB fault handler for faults with VHPT turned off.
     } else {
         /*
          * Forward the page fault to address space page fault handler.
          */
         page_table_unlock(AS, true);
-        if (as_page_fault(va, istate) == AS_PF_FAULT) {
+        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
             panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+        }
+    }
+}
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
  */
 void data_dirty_bit_fault(__u64 vector, istate_t *istate)
+{
+    region_register rr;
+    rid_t rid;
+    __address va;
     pte_t *t;
+    va = istate->cr_ifa;    /* faulting address */
+    rr.word = rr_read(VA2VRN(va));
+    rid = rr.map.rid;
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, istate->cr_ifa);
+    t = page_mapping_find(AS, va);
     ASSERT(t && t->p);
-    if (t && t->p) {
+    if (t && t->p && t->w) {
         /*
          * Update the Dirty bit in page tables and reinsert
          * the mapping into DTC.
          */
         t->d = true;
         dtc_pte_copy(t);
+    } else {
+        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+            t->d = true;
+            dtc_pte_copy(t);
+        }
+    }
     page_table_unlock(AS, true);
+}
 /** Instruction access bit fault handler.
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
  */
 void instruction_access_bit_fault(__u64 vector, istate_t *istate)
+{
+    region_register rr;
+    rid_t rid;
+    __address va;
     pte_t *t;
+    va = istate->cr_ifa;    /* faulting address */
+    rr.word = rr_read(VA2VRN(va));
+    rid = rr.map.rid;
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, istate->cr_ifa);
+    t = page_mapping_find(AS, va);
     ASSERT(t && t->p);
-    if (t && t->p) {
+    if (t && t->p && t->x) {
         /*
          * Update the Accessed bit in page tables and reinsert
          * the mapping into ITC.
          */
         t->a = true;
         itc_pte_copy(t);
+    } else {
+        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+            t->a = true;
+            itc_pte_copy(t);
+        }
+    }
     page_table_unlock(AS, true);
+}
 /** Data access bit fault handler.
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
  */
 void data_access_bit_fault(__u64 vector, istate_t *istate)
+{
+    region_register rr;
+    rid_t rid;
+    __address va;
     pte_t *t;
+    va = istate->cr_ifa;    /* faulting address */
+    rr.word = rr_read(VA2VRN(va));
+    rid = rr.map.rid;
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, istate->cr_ifa);
+    t = page_mapping_find(AS, va);
     ASSERT(t && t->p);
     if (t && t->p) {
         /*
          * Update the Accessed bit in page tables and reinsert
          * the mapping into DTC.
          */
         t->a = true;
         dtc_pte_copy(t);
+    } else {
+        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+            t->a = true;
+            itc_pte_copy(t);
+        }
+    }
     page_table_unlock(AS, true);
+}
 /** Page not present fault handler.
  * @param istate Structure with saved interruption state.
  */
 void page_not_present(__u64 vector, istate_t *istate)
+{
     region_register rr;
+    rid_t rid;
     __address va;
     pte_t *t;
     va = istate->cr_ifa;    /* faulting address */
+    rr.word = rr_read(VA2VRN(va));
+    rid = rr.map.rid;
     page_table_lock(AS, true);
     t = page_mapping_find(AS, va);
     ASSERT(t);
     if (t->p) {
         else
             dtc_pte_copy(t);
         page_table_unlock(AS, true);
     } else {
         page_table_unlock(AS, true);
-        if (as_page_fault(va, istate) == AS_PF_FAULT) {
+        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-            panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rr.map.rid);
+            panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rid);
+        }
+    }
+}

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/mm/tlb.c – Rev 1288 → 1411