WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/mm/page.c


/*
 * Copyright (C) 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup ia64mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/page.h>
#include <genarch/mm/page_ht.h>
#include <mm/asid.h>
#include <arch/mm/asid.h>
#include <arch/mm/vhpt.h>
#include <arch/types.h>
#include <typedefs.h>
#include <print.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <config.h>
#include <panic.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
 
static void set_environment(void);
 
/** Initialize ia64 virtual address translation subsystem. */
void page_arch_init(void)
{
    page_mapping_operations = &ht_mapping_operations;
    pk_disable();
    set_environment();
}
 
/** Initialize VHPT and region registers. */
void set_environment(void)
{
    region_register rr;
    pta_register pta;  
    int i;
#ifdef CONFIG_VHPT  
    __address vhpt_base;
#endif
 
    /*
     * First set up kernel region register.
     * This is redundant (see start.S) but we keep it here just for sure.
     */
    rr.word = rr_read(VRN_KERNEL);
    rr.map.ve = 0;                  /* disable VHPT walker */
    rr.map.ps = PAGE_WIDTH;
    rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
    rr_write(VRN_KERNEL, rr.word);
    srlz_i();
    srlz_d();
 
    /*
     * And setup the rest of region register.
     */
    for(i = 0; i < REGION_REGISTERS; i++) {
        /* skip kernel rr */
        if (i == VRN_KERNEL)
            continue;
   
        rr.word = rr_read(i);
        rr.map.ve = 0;      /* disable VHPT walker */
        rr.map.rid = RID_KERNEL;
        rr.map.ps = PAGE_WIDTH;
        rr_write(i, rr.word);
        srlz_i();
        srlz_d();
    }
 
#ifdef CONFIG_VHPT  
    vhpt_base = vhpt_set_up();
#endif
    /*
     * Set up PTA register.
     */
    pta.word = pta_read();
#ifndef CONFIG_VHPT
    pta.map.ve = 0;                   /* disable VHPT walker */
    pta.map.base = 0 >> PTA_BASE_SHIFT;
#else
    pta.map.ve = 1;                   /* enable VHPT walker */
    pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
#endif
    pta.map.vf = 1;                   /* large entry format */
    pta.map.size = VHPT_WIDTH;
    pta_write(pta.word);
    srlz_i();
    srlz_d();
}
 
/** Calculate address of collision chain from VPN and ASID.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return VHPT entry address.
 */
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
{
    region_register rr_save, rr;
    index_t vrn;
    rid_t rid;
    vhpt_entry_t *v;
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compute thash and return.
         */
        v = (vhpt_entry_t *) thash(page);
        return v;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    v = (vhpt_entry_t *) thash(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return v;
}
 
/** Compare ASID and VPN against PTE.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return True if page and asid match the page and asid of t, false otherwise.
 */
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    bool match;
 
    ASSERT(v);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compare ttag with t and return.
         */
        return ttag(page) == v->present.tag.tag_word;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    match = (ttag(page) == v->present.tag.tag_word);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return match;      
}
 
/** Set up one VHPT entry.
 *
 * @param t VHPT entry to be set up.
 * @param page Virtual address of the page mapped by the entry.
 * @param asid Address space identifier of the address space to which page belongs.
 * @param frame Physical address of the frame to wich page is mapped.
 * @param flags Different flags for the mapping.
 */
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    __u64 tag;
 
    ASSERT(v);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    /*
     * Compute ttag.
     */
    rr_save.word = rr_read(vrn);
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    tag = ttag(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
   
    /*
     * Clear the entry.
     */
    v->word[0] = 0;
    v->word[1] = 0;
    v->word[2] = 0;
    v->word[3] = 0;
   
    v->present.p = true;
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
    v->present.a = false;   /* not accessed */
    v->present.d = false;   /* not dirty */
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
    v->present.ppn = frame >> PPN_SHIFT;
    v->present.ed = false;  /* exception not deffered */
    v->present.ps = PAGE_WIDTH;
    v->present.key = 0;
    v->present.tag.tag_word = tag;
}
 
 /** @}
 */
 
 

Rev 1210	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
-		30	/** @addtogroup ia64mm
-		31	* @{
-		32	*/
-		33	/** @file
-		34	*/
-		35
30	#include <arch/mm/page.h>	36	#include <arch/mm/page.h>
31	#include <genarch/mm/page_ht.h>	37	#include <genarch/mm/page_ht.h>
32	#include <mm/asid.h>	38	#include <mm/asid.h>
33	#include <arch/mm/asid.h>	39	#include <arch/mm/asid.h>
34	#include <arch/mm/vhpt.h>	40	#include <arch/mm/vhpt.h>
35	#include <arch/types.h>	41	#include <arch/types.h>
36	#include <typedefs.h>	42	#include <typedefs.h>
37	#include <print.h>	43	#include <print.h>
38	#include <mm/page.h>	44	#include <mm/page.h>
39	#include <mm/frame.h>	45	#include <mm/frame.h>
40	#include <config.h>	46	#include <config.h>
41	#include <panic.h>	47	#include <panic.h>
42	#include <arch/asm.h>	48	#include <arch/asm.h>
43	#include <arch/barrier.h>	49	#include <arch/barrier.h>
44	#include <memstr.h>	50	#include <memstr.h>
45		51
46	static void set_environment(void);	52	static void set_environment(void);
47		53
48	/** Initialize ia64 virtual address translation subsystem. */	54	/** Initialize ia64 virtual address translation subsystem. */
49	void page_arch_init(void)	55	void page_arch_init(void)
50	{	56	{
51	page_mapping_operations = &ht_mapping_operations;	57	page_mapping_operations = &ht_mapping_operations;
52	pk_disable();	58	pk_disable();
53	set_environment();	59	set_environment();
54	}	60	}
55		61
56	/** Initialize VHPT and region registers. */	62	/** Initialize VHPT and region registers. */
57	void set_environment(void)	63	void set_environment(void)
58	{	64	{
59	region_register rr;	65	region_register rr;
60	pta_register pta;	66	pta_register pta;
61	int i;	67	int i;
62	#ifdef CONFIG_VHPT	68	#ifdef CONFIG_VHPT
63	__address vhpt_base;	69	__address vhpt_base;
64	#endif	70	#endif
65		71
66	/*	72	/*
67	* First set up kernel region register.	73	* First set up kernel region register.
68	* This is redundant (see start.S) but we keep it here just for sure.	74	* This is redundant (see start.S) but we keep it here just for sure.
69	*/	75	*/
70	rr.word = rr_read(VRN_KERNEL);	76	rr.word = rr_read(VRN_KERNEL);
71	rr.map.ve = 0; /* disable VHPT walker */	77	rr.map.ve = 0; /* disable VHPT walker */
72	rr.map.ps = PAGE_WIDTH;	78	rr.map.ps = PAGE_WIDTH;
73	rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);	79	rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
74	rr_write(VRN_KERNEL, rr.word);	80	rr_write(VRN_KERNEL, rr.word);
75	srlz_i();	81	srlz_i();
76	srlz_d();	82	srlz_d();
77		83
78	/*	84	/*
79	* And setup the rest of region register.	85	* And setup the rest of region register.
80	*/	86	*/
81	for(i = 0; i < REGION_REGISTERS; i++) {	87	for(i = 0; i < REGION_REGISTERS; i++) {
82	/* skip kernel rr */	88	/* skip kernel rr */
83	if (i == VRN_KERNEL)	89	if (i == VRN_KERNEL)
84	continue;	90	continue;
85		91
86	rr.word = rr_read(i);	92	rr.word = rr_read(i);
87	rr.map.ve = 0; /* disable VHPT walker */	93	rr.map.ve = 0; /* disable VHPT walker */
88	rr.map.rid = RID_KERNEL;	94	rr.map.rid = RID_KERNEL;
89	rr.map.ps = PAGE_WIDTH;	95	rr.map.ps = PAGE_WIDTH;
90	rr_write(i, rr.word);	96	rr_write(i, rr.word);
91	srlz_i();	97	srlz_i();
92	srlz_d();	98	srlz_d();
93	}	99	}
94		100
95	#ifdef CONFIG_VHPT	101	#ifdef CONFIG_VHPT
96	vhpt_base = vhpt_set_up();	102	vhpt_base = vhpt_set_up();
97	#endif	103	#endif
98	/*	104	/*
99	* Set up PTA register.	105	* Set up PTA register.
100	*/	106	*/
101	pta.word = pta_read();	107	pta.word = pta_read();
102	#ifndef CONFIG_VHPT	108	#ifndef CONFIG_VHPT
103	pta.map.ve = 0; /* disable VHPT walker */	109	pta.map.ve = 0; /* disable VHPT walker */
104	pta.map.base = 0 >> PTA_BASE_SHIFT;	110	pta.map.base = 0 >> PTA_BASE_SHIFT;
105	#else	111	#else
106	pta.map.ve = 1; /* enable VHPT walker */	112	pta.map.ve = 1; /* enable VHPT walker */
107	pta.map.base = vhpt_base >> PTA_BASE_SHIFT;	113	pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
108	#endif	114	#endif
109	pta.map.vf = 1; /* large entry format */	115	pta.map.vf = 1; /* large entry format */
110	pta.map.size = VHPT_WIDTH;	116	pta.map.size = VHPT_WIDTH;
111	pta_write(pta.word);	117	pta_write(pta.word);
112	srlz_i();	118	srlz_i();
113	srlz_d();	119	srlz_d();
114	}	120	}
115		121
116	/** Calculate address of collision chain from VPN and ASID.	122	/** Calculate address of collision chain from VPN and ASID.
117	*	123	*
118	* Interrupts must be disabled.	124	* Interrupts must be disabled.
119	*	125	*
120	* @param page Address of virtual page including VRN bits.	126	* @param page Address of virtual page including VRN bits.
121	* @param asid Address space identifier.	127	* @param asid Address space identifier.
122	*	128	*
123	* @return VHPT entry address.	129	* @return VHPT entry address.
124	*/	130	*/
125	vhpt_entry_t *vhpt_hash(__address page, asid_t asid)	131	vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
126	{	132	{
127	region_register rr_save, rr;	133	region_register rr_save, rr;
128	index_t vrn;	134	index_t vrn;
129	rid_t rid;	135	rid_t rid;
130	vhpt_entry_t *v;	136	vhpt_entry_t *v;
131		137
132	vrn = page >> VRN_SHIFT;	138	vrn = page >> VRN_SHIFT;
133	rid = ASID2RID(asid, vrn);	139	rid = ASID2RID(asid, vrn);
134		140
135	rr_save.word = rr_read(vrn);	141	rr_save.word = rr_read(vrn);
136	if (rr_save.map.rid == rid) {	142	if (rr_save.map.rid == rid) {
137	/*	143	/*
138	* The RID is already in place, compute thash and return.	144	* The RID is already in place, compute thash and return.
139	*/	145	*/
140	v = (vhpt_entry_t *) thash(page);	146	v = (vhpt_entry_t *) thash(page);
141	return v;	147	return v;
142	}	148	}
143		149
144	/*	150	/*
145	* The RID must be written to some region register.	151	* The RID must be written to some region register.
146	* To speed things up, register indexed by vrn is used.	152	* To speed things up, register indexed by vrn is used.
147	*/	153	*/
148	rr.word = rr_save.word;	154	rr.word = rr_save.word;
149	rr.map.rid = rid;	155	rr.map.rid = rid;
150	rr_write(vrn, rr.word);	156	rr_write(vrn, rr.word);
151	srlz_i();	157	srlz_i();
152	v = (vhpt_entry_t *) thash(page);	158	v = (vhpt_entry_t *) thash(page);
153	rr_write(vrn, rr_save.word);	159	rr_write(vrn, rr_save.word);
154	srlz_i();	160	srlz_i();
155	srlz_d();	161	srlz_d();
156		162
157	return v;	163	return v;
158	}	164	}
159		165
160	/** Compare ASID and VPN against PTE.	166	/** Compare ASID and VPN against PTE.
161	*	167	*
162	* Interrupts must be disabled.	168	* Interrupts must be disabled.
163	*	169	*
164	* @param page Address of virtual page including VRN bits.	170	* @param page Address of virtual page including VRN bits.
165	* @param asid Address space identifier.	171	* @param asid Address space identifier.
166	*	172	*
167	* @return True if page and asid match the page and asid of t, false otherwise.	173	* @return True if page and asid match the page and asid of t, false otherwise.
168	*/	174	*/
169	bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)	175	bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
170	{	176	{
171	region_register rr_save, rr;	177	region_register rr_save, rr;
172	index_t vrn;	178	index_t vrn;
173	rid_t rid;	179	rid_t rid;
174	bool match;	180	bool match;
175		181
176	ASSERT(v);	182	ASSERT(v);
177		183
178	vrn = page >> VRN_SHIFT;	184	vrn = page >> VRN_SHIFT;
179	rid = ASID2RID(asid, vrn);	185	rid = ASID2RID(asid, vrn);
180		186
181	rr_save.word = rr_read(vrn);	187	rr_save.word = rr_read(vrn);
182	if (rr_save.map.rid == rid) {	188	if (rr_save.map.rid == rid) {
183	/*	189	/*
184	* The RID is already in place, compare ttag with t and return.	190	* The RID is already in place, compare ttag with t and return.
185	*/	191	*/
186	return ttag(page) == v->present.tag.tag_word;	192	return ttag(page) == v->present.tag.tag_word;
187	}	193	}
188		194
189	/*	195	/*
190	* The RID must be written to some region register.	196	* The RID must be written to some region register.
191	* To speed things up, register indexed by vrn is used.	197	* To speed things up, register indexed by vrn is used.
192	*/	198	*/
193	rr.word = rr_save.word;	199	rr.word = rr_save.word;
194	rr.map.rid = rid;	200	rr.map.rid = rid;
195	rr_write(vrn, rr.word);	201	rr_write(vrn, rr.word);
196	srlz_i();	202	srlz_i();
197	match = (ttag(page) == v->present.tag.tag_word);	203	match = (ttag(page) == v->present.tag.tag_word);
198	rr_write(vrn, rr_save.word);	204	rr_write(vrn, rr_save.word);
199	srlz_i();	205	srlz_i();
200	srlz_d();	206	srlz_d();
201		207
202	return match;	208	return match;
203	}	209	}
204		210
205	/** Set up one VHPT entry.	211	/** Set up one VHPT entry.
206	*	212	*
207	* @param t VHPT entry to be set up.	213	* @param t VHPT entry to be set up.
208	* @param page Virtual address of the page mapped by the entry.	214	* @param page Virtual address of the page mapped by the entry.
209	* @param asid Address space identifier of the address space to which page belongs.	215	* @param asid Address space identifier of the address space to which page belongs.
210	* @param frame Physical address of the frame to wich page is mapped.	216	* @param frame Physical address of the frame to wich page is mapped.
211	* @param flags Different flags for the mapping.	217	* @param flags Different flags for the mapping.
212	*/	218	*/
213	void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)	219	void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
214	{	220	{
215	region_register rr_save, rr;	221	region_register rr_save, rr;
216	index_t vrn;	222	index_t vrn;
217	rid_t rid;	223	rid_t rid;
218	__u64 tag;	224	__u64 tag;
219		225
220	ASSERT(v);	226	ASSERT(v);
221		227
222	vrn = page >> VRN_SHIFT;	228	vrn = page >> VRN_SHIFT;
223	rid = ASID2RID(asid, vrn);	229	rid = ASID2RID(asid, vrn);
224		230
225	/*	231	/*
226	* Compute ttag.	232	* Compute ttag.
227	*/	233	*/
228	rr_save.word = rr_read(vrn);	234	rr_save.word = rr_read(vrn);
229	rr.word = rr_save.word;	235	rr.word = rr_save.word;
230	rr.map.rid = rid;	236	rr.map.rid = rid;
231	rr_write(vrn, rr.word);	237	rr_write(vrn, rr.word);
232	srlz_i();	238	srlz_i();
233	tag = ttag(page);	239	tag = ttag(page);
234	rr_write(vrn, rr_save.word);	240	rr_write(vrn, rr_save.word);
235	srlz_i();	241	srlz_i();
236	srlz_d();	242	srlz_d();
237		243
238	/*	244	/*
239	* Clear the entry.	245	* Clear the entry.
240	*/	246	*/
241	v->word[0] = 0;	247	v->word[0] = 0;
242	v->word[1] = 0;	248	v->word[1] = 0;
243	v->word[2] = 0;	249	v->word[2] = 0;
244	v->word[3] = 0;	250	v->word[3] = 0;
245		251
246	v->present.p = true;	252	v->present.p = true;
247	v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;	253	v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
248	v->present.a = false; /* not accessed */	254	v->present.a = false; /* not accessed */
249	v->present.d = false; /* not dirty */	255	v->present.d = false; /* not dirty */
250	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;	256	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
251	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;	257	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
252	v->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;	258	v->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
253	v->present.ppn = frame >> PPN_SHIFT;	259	v->present.ppn = frame >> PPN_SHIFT;
254	v->present.ed = false; /* exception not deffered */	260	v->present.ed = false; /* exception not deffered */
255	v->present.ps = PAGE_WIDTH;	261	v->present.ps = PAGE_WIDTH;
256	v->present.key = 0;	262	v->present.key = 0;
257	v->present.tag.tag_word = tag;	263	v->present.tag.tag_word = tag;
258	}	264	}
-		265
-		266	/** @}
-		267	*/
-		268
259		269

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/mm/page.c – Rev 1210 → 1702