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#include <arch/stack.h>
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#include <arch/stack.h>
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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <align.h>
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#include <align.h>
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#define STACK_ITEMS		13
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#define STACK_ITEMS		14
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#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
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#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
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#if (STACK_ITEMS % 2 == 0)
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#if (STACK_ITEMS % 2 == 0)
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#	define STACK_FRAME_BIAS	8
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#	define STACK_FRAME_BIAS	8
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#else
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#else
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	mov r27 = ar.rnat
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	mov r27 = ar.rnat
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	mov r28 = ar.bspstore ;;
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	mov r28 = ar.bspstore ;;
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	/* assume kernel backing store */
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	/* assume kernel backing store */
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	/* mov ar.bspstore = r28 ;; */
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	mov ar.bspstore = r28 ;;
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	mov r29 = ar.bsp
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	mov r29 = ar.bsp
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	st8 [r31] = r27, -8 ;;	/* save ar.rnat */
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	st8 [r31] = r27, -8 ;;	/* save ar.rnat */
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	st8 [r31] = r28, -8 ;;	/* save new value written to ar.bspstore */
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	st8 [r31] = r28, -8 ;;	/* save ar.bspstore */
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	st8 [r31] = r28, -8 ;;	/* save ar.bspstore */
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	st8 [r31] = r29, -8 	/* save ar.bsp */
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	st8 [r31] = r29, -8 	/* save ar.bsp */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	mov ar.rsc = r24	/* restore RSE's setting */
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    /* 16. RSE switch to interrupted context */
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    /* 16. RSE switch to interrupted context */
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	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
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	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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	mov r28 = ar.bspstore   	/* calculate loadrs (step 2) */
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	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
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	ld8 r29 = [r31], +8 ;;		/* load ar.bsp */
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	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
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	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
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	sub r27 = r29 , r28 ;;
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	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
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	shl r27 = r27, 16
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	shl r27 = r27, 16
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	mov r24 = ar.rsc ;;
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	mov r24 = ar.rsc ;;
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	and r30 = ~3, r24 ;;
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	and r30 = ~3, r24 ;;
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	or  r24 = r30 , r27 ;;
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	or  r24 = r30 , r27 ;;
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	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
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	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
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	loadrs 				/* (step 3) */
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	loadrs 				/* (step 3) */
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	ld8 r28 = [r31], +8 ;;    	/* load ar.bspstore */
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	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
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	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
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	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
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	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
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	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
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	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
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	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
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	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
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	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
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	mov ar.bspstore = r29 ;;	/* (step 4) */
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	/* mov ar.rnat = r27 */		/* (step 5) */
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	mov ar.rnat = r27		/* (step 5) */
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	mov ar.pfs = r25		/* (step 6) */
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	mov ar.pfs = r25		/* (step 6) */
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	mov cr.ifs = r26
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	mov cr.ifs = r26
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	mov ar.rsc = r24		/* (step 7) */
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	mov ar.rsc = r24		/* (step 7) */