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| 1 | # |
1 | # |
| 2 | # Copyright (C) 2005 Jakub Vana |
2 | # Copyright (C) 2005 Jakub Vana |
| 3 | # Copyright (C) 2005 Jakub Jermar |
3 | # Copyright (C) 2005 Jakub Jermar |
| 4 | # All rights reserved. |
4 | # All rights reserved. |
| 5 | # |
5 | # |
| 6 | # Redistribution and use in source and binary forms, with or without |
6 | # Redistribution and use in source and binary forms, with or without |
| 7 | # modification, are permitted provided that the following conditions |
7 | # modification, are permitted provided that the following conditions |
| 8 | # are met: |
8 | # are met: |
| 9 | # |
9 | # |
| 10 | # - Redistributions of source code must retain the above copyright |
10 | # - Redistributions of source code must retain the above copyright |
| 11 | # notice, this list of conditions and the following disclaimer. |
11 | # notice, this list of conditions and the following disclaimer. |
| 12 | # - Redistributions in binary form must reproduce the above copyright |
12 | # - Redistributions in binary form must reproduce the above copyright |
| 13 | # notice, this list of conditions and the following disclaimer in the |
13 | # notice, this list of conditions and the following disclaimer in the |
| 14 | # documentation and/or other materials provided with the distribution. |
14 | # documentation and/or other materials provided with the distribution. |
| 15 | # - The name of the author may not be used to endorse or promote products |
15 | # - The name of the author may not be used to endorse or promote products |
| 16 | # derived from this software without specific prior written permission. |
16 | # derived from this software without specific prior written permission. |
| 17 | # |
17 | # |
| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | # |
28 | # |
| 29 | 29 | ||
| 30 | #include <arch/stack.h> |
30 | #include <arch/stack.h> |
| 31 | #include <arch/register.h> |
31 | #include <arch/register.h> |
| 32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
| 33 | #include <align.h> |
33 | #include <align.h> |
| 34 | 34 | ||
| 35 | - | ||
| 36 | #define FRS_TO_SAVE 30 |
35 | #define FRS_TO_SAVE 30 |
| 37 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
36 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
| 38 | //#define STACK_ITEMS 19 |
- | |
| 39 | /* 30*2 for FPU registers */ |
- | |
| 40 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
37 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
| 41 | 38 | ||
| 42 | #if (STACK_ITEMS % 2 == 0) |
39 | #if (STACK_ITEMS % 2 == 0) |
| 43 | # define STACK_FRAME_BIAS 8 |
40 | # define STACK_FRAME_BIAS 8 |
| 44 | #else |
41 | #else |
| 45 | # define STACK_FRAME_BIAS 16 |
42 | # define STACK_FRAME_BIAS 16 |
| 46 | #endif |
43 | #endif |
| 47 | 44 | ||
| 48 | /** Partitioning of bank 0 registers. */ |
45 | /** Partitioning of bank 0 registers. */ |
| 49 | #define R_OFFS r16 |
46 | #define R_OFFS r16 |
| 50 | #define R_HANDLER r17 |
47 | #define R_HANDLER r17 |
| 51 | #define R_RET r18 |
48 | #define R_RET r18 |
| 52 | #define R_TMP r19 |
49 | #define R_TMP r19 |
| 53 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
50 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
| 54 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
51 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
| 55 | 52 | ||
| 56 | /** Heavyweight interrupt handler |
53 | /** Heavyweight interrupt handler |
| 57 | * |
54 | * |
| 58 | * This macro roughly follows steps from 1 to 19 described in |
55 | * This macro roughly follows steps from 1 to 19 described in |
| 59 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
56 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
| 60 | * |
57 | * |
| 61 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
58 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
| 62 | * This goal is achieved by using procedure calls after RSE becomes operational. |
59 | * This goal is achieved by using procedure calls after RSE becomes operational. |
| 63 | * |
60 | * |
| 64 | * Some steps are skipped (enabling and disabling interrupts). |
61 | * Some steps are skipped (enabling and disabling interrupts). |
| 65 | * |
62 | * |
| 66 | * @param offs Offset from the beginning of IVT. |
63 | * @param offs Offset from the beginning of IVT. |
| 67 | * @param handler Interrupt handler address. |
64 | * @param handler Interrupt handler address. |
| 68 | */ |
65 | */ |
| 69 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
66 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
| 70 | .org ivt + \offs |
67 | .org ivt + \offs |
| 71 | mov R_OFFS = \offs |
68 | mov R_OFFS = \offs |
| 72 | movl R_HANDLER = \handler ;; |
69 | movl R_HANDLER = \handler ;; |
| 73 | br heavyweight_handler |
70 | br heavyweight_handler |
| 74 | .endm |
71 | .endm |
| 75 | 72 | ||
| 76 | .global heavyweight_handler |
73 | .global heavyweight_handler |
| 77 | heavyweight_handler: |
74 | heavyweight_handler: |
| 78 | /* 1. copy interrupt registers into bank 0 */ |
75 | /* 1. copy interrupt registers into bank 0 */ |
| 79 | 76 | ||
| 80 | /* |
77 | /* |
| 81 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
78 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
| 82 | */ |
79 | */ |
| 83 | 80 | ||
| 84 | /* Set up FPU as in interrupted context. */ |
81 | /* Set up FPU as in interrupted context. */ |
| 85 | mov r24 = psr |
82 | mov r24 = psr |
| 86 | mov r25 = cr.ipsr |
83 | mov r25 = cr.ipsr |
| 87 | mov r26 = PSR_DFH_MASK |
84 | mov r26 = PSR_DFH_MASK |
| 88 | mov r27 = ~PSR_DFH_MASK ;; |
85 | mov r27 = ~PSR_DFH_MASK ;; |
| 89 | and r26 = r25, r26 |
86 | and r26 = r25, r26 |
| 90 | and r24 = r24, r27;; |
87 | and r24 = r24, r27;; |
| 91 | or r24 = r24, r26;; |
88 | or r24 = r24, r26;; |
| 92 | mov psr.l = r24;; |
89 | mov psr.l = r24;; |
| 93 | srlz.i |
90 | srlz.i |
| 94 | srlz.d;; |
91 | srlz.d;; |
| 95 | 92 | ||
| 96 | mov r24 = cr.iip |
93 | mov r24 = cr.iip |
| 97 | mov r25 = cr.ipsr |
94 | mov r25 = cr.ipsr |
| 98 | mov r26 = cr.iipa |
95 | mov r26 = cr.iipa |
| 99 | mov r27 = cr.isr |
96 | mov r27 = cr.isr |
| 100 | mov r28 = cr.ifa |
97 | mov r28 = cr.ifa |
| 101 | 98 | ||
| 102 | /* 2. preserve predicate register into bank 0 */ |
99 | /* 2. preserve predicate register into bank 0 */ |
| 103 | mov r29 = pr ;; |
100 | mov r29 = pr ;; |
| 104 | 101 | ||
| 105 | /* 3. switch to kernel memory stack */ |
102 | /* 3. switch to kernel memory stack */ |
| 106 | mov r30 = cr.ipsr |
103 | mov r30 = cr.ipsr |
| 107 | shr.u r31 = r12, VRN_SHIFT ;; |
104 | shr.u r31 = r12, VRN_SHIFT ;; |
| 108 | 105 | ||
| 109 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
106 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
| 110 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
107 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
| 111 | 108 | ||
| 112 | /* |
109 | /* |
| 113 | * Set p3 to true if the interrupted context executed in kernel mode. |
110 | * Set p3 to true if the interrupted context executed in kernel mode. |
| 114 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
111 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
| 115 | */ |
112 | */ |
| 116 | cmp.eq p3, p4 = r30, r0 ;; |
113 | cmp.eq p3, p4 = r30, r0 ;; |
| 117 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
114 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
| 118 | 115 | ||
| 119 | /* |
116 | /* |
| 120 | * Set p3 to true if the stack register references kernel address space. |
117 | * Set p3 to true if the stack register references kernel address space. |
| 121 | * Set p4 to false if the stack register doesn't reference kernel address space. |
118 | * Set p4 to false if the stack register doesn't reference kernel address space. |
| 122 | */ |
119 | */ |
| 123 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
120 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
| 124 | 121 | ||
| 125 | /* |
122 | /* |
| 126 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
123 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
| 127 | */ |
124 | */ |
| 128 | mov r30 = r12 |
125 | mov r30 = r12 |
| 129 | (p4) mov r12 = R_KSTACK ;; |
126 | (p4) mov r12 = R_KSTACK ;; |
| 130 | 127 | ||
| 131 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
128 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
| 132 | add r12 = -STACK_FRAME_SIZE, r12 |
129 | add r12 = -STACK_FRAME_SIZE, r12 |
| 133 | 130 | ||
| 134 | /* 4. save registers in bank 0 into memory stack */ |
131 | /* 4. save registers in bank 0 into memory stack */ |
| 135 | 132 | ||
| 136 | /* |
133 | /* |
| 137 | * If this is break_instruction handler, |
134 | * If this is break_instruction handler, |
| 138 | * copy input parameters to stack. |
135 | * copy input parameters to stack. |
| 139 | */ |
136 | */ |
| 140 | mov R_TMP = 0x2c00 ;; |
137 | mov R_TMP = 0x2c00 ;; |
| 141 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
138 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
| 142 | 139 | ||
| 143 | /* |
140 | /* |
| 144 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
141 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
| 145 | * Otherwise p6 is false and p5 is true. |
142 | * Otherwise p6 is false and p5 is true. |
| 146 | * Note that p5 is a preserved predicate register and we make use of it. |
143 | * Note that p5 is a preserved predicate register and we make use of it. |
| 147 | */ |
144 | */ |
| 148 | 145 | ||
| 149 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
146 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
| 150 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
147 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
| 151 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
148 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
| 152 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
149 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
| 153 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
150 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
| 154 | (p5) add r31 = -40, r31 ;; |
151 | (p5) add r31 = -40, r31 ;; |
| 155 | 152 | ||
| 156 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
153 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
| 157 | 154 | ||
| 158 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
155 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
| 159 | 156 | ||
| 160 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
157 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
| 161 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
158 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
| 162 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
159 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
| 163 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
160 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
| 164 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
161 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
| 165 | 162 | ||
| 166 | /* 5. RSE switch from interrupted context */ |
163 | /* 5. RSE switch from interrupted context */ |
| 167 | mov r24 = ar.rsc |
164 | mov r24 = ar.rsc |
| 168 | mov r25 = ar.pfs |
165 | mov r25 = ar.pfs |
| 169 | cover |
166 | cover |
| 170 | mov r26 = cr.ifs |
167 | mov r26 = cr.ifs |
| 171 | 168 | ||
| 172 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
169 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
| 173 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
170 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
| 174 | st8 [r31] = r26, -8 /* save ar.ifs */ |
171 | st8 [r31] = r26, -8 /* save ar.ifs */ |
| 175 | 172 | ||
| 176 | and r24 = ~(RSC_PL_MASK), r24 ;; |
173 | and r24 = ~(RSC_PL_MASK), r24 ;; |
| 177 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
174 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
| 178 | mov ar.rsc = r30 ;; /* update RSE state */ |
175 | mov ar.rsc = r30 ;; /* update RSE state */ |
| 179 | 176 | ||
| 180 | mov r27 = ar.rnat |
177 | mov r27 = ar.rnat |
| 181 | mov r28 = ar.bspstore ;; |
178 | mov r28 = ar.bspstore ;; |
| 182 | 179 | ||
| 183 | /* |
180 | /* |
| 184 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
181 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
| 185 | */ |
182 | */ |
| 186 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
183 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
| 187 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
184 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
| 188 | 185 | ||
| 189 | /* |
186 | /* |
| 190 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
187 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
| 191 | */ |
188 | */ |
| 192 | (p1) mov r30 = r28 |
189 | (p1) mov r30 = r28 |
| 193 | (p2) mov r30 = R_KSTACK_BSP ;; |
190 | (p2) mov r30 = R_KSTACK_BSP ;; |
| 194 | (p2) mov ar.bspstore = r30 ;; |
191 | (p2) mov ar.bspstore = r30 ;; |
| 195 | 192 | ||
| 196 | mov r29 = ar.bsp |
193 | mov r29 = ar.bsp |
| 197 | 194 | ||
| 198 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
195 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
| 199 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
196 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
| 200 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
197 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
| 201 | st8 [r31] = r29, -8 /* save ar.bsp */ |
198 | st8 [r31] = r29, -8 /* save ar.bsp */ |
| 202 | 199 | ||
| 203 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
200 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
| 204 | 201 | ||
| 205 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
202 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
| 206 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
203 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
| 207 | br.call.sptk.many b0 = heavyweight_handler_inner |
204 | br.call.sptk.many b0 = heavyweight_handler_inner |
| 208 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
205 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
| 209 | 206 | ||
| 210 | /* 16. RSE switch to interrupted context */ |
207 | /* 16. RSE switch to interrupted context */ |
| 211 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
208 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
| 212 | 209 | ||
| 213 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
210 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
| 214 | 211 | ||
| 215 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
212 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
| 216 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
213 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
| 217 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
214 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
| 218 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
215 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
| 219 | shl r27 = r27, 16 |
216 | shl r27 = r27, 16 |
| 220 | 217 | ||
| 221 | mov r24 = ar.rsc ;; |
218 | mov r24 = ar.rsc ;; |
| 222 | and r30 = ~3, r24 ;; |
219 | and r30 = ~3, r24 ;; |
| 223 | or r24 = r30 , r27 ;; |
220 | or r24 = r30 , r27 ;; |
| 224 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
221 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
| 225 | 222 | ||
| 226 | loadrs /* (step 3) */ |
223 | loadrs /* (step 3) */ |
| 227 | 224 | ||
| 228 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
225 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
| 229 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
226 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
| 230 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
227 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
| 231 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
228 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
| 232 | 229 | ||
| 233 | mov ar.bspstore = r29 ;; /* (step 4) */ |
230 | mov ar.bspstore = r29 ;; /* (step 4) */ |
| 234 | mov ar.rnat = r27 /* (step 5) */ |
231 | mov ar.rnat = r27 /* (step 5) */ |
| 235 | 232 | ||
| 236 | mov ar.pfs = r25 /* (step 6) */ |
233 | mov ar.pfs = r25 /* (step 6) */ |
| 237 | mov cr.ifs = r26 |
234 | mov cr.ifs = r26 |
| 238 | 235 | ||
| 239 | mov ar.rsc = r24 /* (step 7) */ |
236 | mov ar.rsc = r24 /* (step 7) */ |
| 240 | 237 | ||
| 241 | /* 17. restore interruption state from memory stack */ |
238 | /* 17. restore interruption state from memory stack */ |
| 242 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
239 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
| 243 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
240 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
| 244 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
241 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
| 245 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
242 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
| 246 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
243 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
| 247 | 244 | ||
| 248 | mov cr.iip = r24;; |
245 | mov cr.iip = r24;; |
| 249 | mov cr.iipa = r26 |
246 | mov cr.iipa = r26 |
| 250 | mov cr.isr = r27 |
247 | mov cr.isr = r27 |
| 251 | mov cr.ifa = r28 |
248 | mov cr.ifa = r28 |
| 252 | 249 | ||
| 253 | /* Set up FPU as in exception. */ |
250 | /* Set up FPU as in exception. */ |
| 254 | mov r24 = psr |
251 | mov r24 = psr |
| 255 | mov r26 = PSR_DFH_MASK |
252 | mov r26 = PSR_DFH_MASK |
| 256 | mov r27 = ~PSR_DFH_MASK ;; |
253 | mov r27 = ~PSR_DFH_MASK ;; |
| 257 | and r25 = r25, r27 |
254 | and r25 = r25, r27 |
| 258 | and r24 = r24, r26 ;; |
255 | and r24 = r24, r26 ;; |
| 259 | or r25 = r25, r24;; |
256 | or r25 = r25, r24;; |
| 260 | mov cr.ipsr = r25 |
257 | mov cr.ipsr = r25 |
| 261 | 258 | ||
| 262 | /* 18. restore predicate registers from memory stack */ |
259 | /* 18. restore predicate registers from memory stack */ |
| 263 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
260 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
| 264 | mov pr = r29 |
261 | mov pr = r29 |
| 265 | 262 | ||
| 266 | /* 19. return from interruption */ |
263 | /* 19. return from interruption */ |
| 267 | ld8 r12 = [r31] /* load stack pointer */ |
264 | ld8 r12 = [r31] /* load stack pointer */ |
| 268 | rfi ;; |
265 | rfi ;; |
| 269 | 266 | ||
| 270 | .global heavyweight_handler_inner |
267 | .global heavyweight_handler_inner |
| 271 | heavyweight_handler_inner: |
268 | heavyweight_handler_inner: |
| 272 | /* |
269 | /* |
| 273 | * From this point, the rest of the interrupted context |
270 | * From this point, the rest of the interrupted context |
| 274 | * will be preserved in stacked registers and backing store. |
271 | * will be preserved in stacked registers and backing store. |
| 275 | */ |
272 | */ |
| 276 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
273 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
| 277 | 274 | ||
| 278 | /* bank 0 is going to be shadowed, copy essential data from there */ |
275 | /* bank 0 is going to be shadowed, copy essential data from there */ |
| 279 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
276 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
| 280 | mov loc2 = R_HANDLER |
277 | mov loc2 = R_HANDLER |
| 281 | mov out0 = R_OFFS |
278 | mov out0 = R_OFFS |
| 282 | 279 | ||
| 283 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
280 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
| 284 | 281 | ||
| 285 | /* 6. switch to bank 1 and reenable PSR.ic */ |
282 | /* 6. switch to bank 1 and reenable PSR.ic */ |
| 286 | ssm PSR_IC_MASK |
283 | ssm PSR_IC_MASK |
| 287 | bsw.1 ;; |
284 | bsw.1 ;; |
| 288 | srlz.d |
285 | srlz.d |
| 289 | 286 | ||
| 290 | /* 7. preserve branch and application registers */ |
287 | /* 7. preserve branch and application registers */ |
| 291 | mov loc3 = ar.unat |
288 | mov loc3 = ar.unat |
| 292 | mov loc4 = ar.lc |
289 | mov loc4 = ar.lc |
| 293 | mov loc5 = ar.ec |
290 | mov loc5 = ar.ec |
| 294 | mov loc6 = ar.ccv |
291 | mov loc6 = ar.ccv |
| 295 | mov loc7 = ar.csd |
292 | mov loc7 = ar.csd |
| 296 | mov loc8 = ar.ssd |
293 | mov loc8 = ar.ssd |
| 297 | 294 | ||
| 298 | mov loc9 = b0 |
295 | mov loc9 = b0 |
| 299 | mov loc10 = b1 |
296 | mov loc10 = b1 |
| 300 | mov loc11 = b2 |
297 | mov loc11 = b2 |
| 301 | mov loc12 = b3 |
298 | mov loc12 = b3 |
| 302 | mov loc13 = b4 |
299 | mov loc13 = b4 |
| 303 | mov loc14 = b5 |
300 | mov loc14 = b5 |
| 304 | mov loc15 = b6 |
301 | mov loc15 = b6 |
| 305 | mov loc16 = b7 |
302 | mov loc16 = b7 |
| 306 | 303 | ||
| 307 | /* 8. preserve general and floating-point registers */ |
304 | /* 8. preserve general and floating-point registers */ |
| 308 | mov loc17 = r1 |
305 | mov loc17 = r1 |
| 309 | mov loc18 = r2 |
306 | mov loc18 = r2 |
| 310 | mov loc19 = r3 |
307 | mov loc19 = r3 |
| 311 | mov loc20 = r4 |
308 | mov loc20 = r4 |
| 312 | mov loc21 = r5 |
309 | mov loc21 = r5 |
| 313 | mov loc22 = r6 |
310 | mov loc22 = r6 |
| 314 | mov loc23 = r7 |
311 | mov loc23 = r7 |
| 315 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
312 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
| 316 | mov loc25 = r9 |
313 | mov loc25 = r9 |
| 317 | mov loc26 = r10 |
314 | mov loc26 = r10 |
| 318 | mov loc27 = r11 |
315 | mov loc27 = r11 |
| 319 | /* skip r12 (stack pointer) */ |
316 | /* skip r12 (stack pointer) */ |
| 320 | mov loc28 = r13 |
317 | mov loc28 = r13 |
| 321 | mov loc29 = r14 |
318 | mov loc29 = r14 |
| 322 | mov loc30 = r15 |
319 | mov loc30 = r15 |
| 323 | mov loc31 = r16 |
320 | mov loc31 = r16 |
| 324 | mov loc32 = r17 |
321 | mov loc32 = r17 |
| 325 | mov loc33 = r18 |
322 | mov loc33 = r18 |
| 326 | mov loc34 = r19 |
323 | mov loc34 = r19 |
| 327 | mov loc35 = r20 |
324 | mov loc35 = r20 |
| 328 | mov loc36 = r21 |
325 | mov loc36 = r21 |
| 329 | mov loc37 = r22 |
326 | mov loc37 = r22 |
| 330 | mov loc38 = r23 |
327 | mov loc38 = r23 |
| 331 | mov loc39 = r24 |
328 | mov loc39 = r24 |
| 332 | mov loc40 = r25 |
329 | mov loc40 = r25 |
| 333 | mov loc41 = r26 |
330 | mov loc41 = r26 |
| 334 | mov loc42 = r27 |
331 | mov loc42 = r27 |
| 335 | mov loc43 = r28 |
332 | mov loc43 = r28 |
| 336 | mov loc44 = r29 |
333 | mov loc44 = r29 |
| 337 | mov loc45 = r30 |
334 | mov loc45 = r30 |
| 338 | mov loc46 = r31 |
335 | mov loc46 = r31 |
| 339 | 336 | ||
| 340 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
337 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
| 341 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
338 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
| 342 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
339 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
| 343 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
340 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
| 344 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
341 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
| 345 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
342 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
| 346 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
343 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
| 347 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
344 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
| 348 | 345 | ||
| 349 | stf.spill [r26] = f2, 0x80 |
346 | stf.spill [r26] = f2, 0x80 |
| 350 | stf.spill [r27] = f3, 0x80 |
347 | stf.spill [r27] = f3, 0x80 |
| 351 | stf.spill [r28] = f4, 0x80 |
348 | stf.spill [r28] = f4, 0x80 |
| 352 | stf.spill [r29] = f5, 0x80 |
349 | stf.spill [r29] = f5, 0x80 |
| 353 | stf.spill [r30] = f6, 0x80 |
350 | stf.spill [r30] = f6, 0x80 |
| 354 | stf.spill [r31] = f7, 0x80 ;; |
351 | stf.spill [r31] = f7, 0x80 ;; |
| 355 | 352 | ||
| 356 | stf.spill [r24] = f8, 0x80 |
353 | stf.spill [r24] = f8, 0x80 |
| 357 | stf.spill [r25] = f9, 0x80 |
354 | stf.spill [r25] = f9, 0x80 |
| 358 | stf.spill [r26] = f10, 0x80 |
355 | stf.spill [r26] = f10, 0x80 |
| 359 | stf.spill [r27] = f11, 0x80 |
356 | stf.spill [r27] = f11, 0x80 |
| 360 | stf.spill [r28] = f12, 0x80 |
357 | stf.spill [r28] = f12, 0x80 |
| 361 | stf.spill [r29] = f13, 0x80 |
358 | stf.spill [r29] = f13, 0x80 |
| 362 | stf.spill [r30] = f14, 0x80 |
359 | stf.spill [r30] = f14, 0x80 |
| 363 | stf.spill [r31] = f15, 0x80 ;; |
360 | stf.spill [r31] = f15, 0x80 ;; |
| 364 | 361 | ||
| 365 | stf.spill [r24] = f16, 0x80 |
362 | stf.spill [r24] = f16, 0x80 |
| 366 | stf.spill [r25] = f17, 0x80 |
363 | stf.spill [r25] = f17, 0x80 |
| 367 | stf.spill [r26] = f18, 0x80 |
364 | stf.spill [r26] = f18, 0x80 |
| 368 | stf.spill [r27] = f19, 0x80 |
365 | stf.spill [r27] = f19, 0x80 |
| 369 | stf.spill [r28] = f20, 0x80 |
366 | stf.spill [r28] = f20, 0x80 |
| 370 | stf.spill [r29] = f21, 0x80 |
367 | stf.spill [r29] = f21, 0x80 |
| 371 | stf.spill [r30] = f22, 0x80 |
368 | stf.spill [r30] = f22, 0x80 |
| 372 | stf.spill [r31] = f23, 0x80 ;; |
369 | stf.spill [r31] = f23, 0x80 ;; |
| 373 | 370 | ||
| 374 | stf.spill [r24] = f24, 0x80 |
371 | stf.spill [r24] = f24, 0x80 |
| 375 | stf.spill [r25] = f25, 0x80 |
372 | stf.spill [r25] = f25, 0x80 |
| 376 | stf.spill [r26] = f26, 0x80 |
373 | stf.spill [r26] = f26, 0x80 |
| 377 | stf.spill [r27] = f27, 0x80 |
374 | stf.spill [r27] = f27, 0x80 |
| 378 | stf.spill [r28] = f28, 0x80 |
375 | stf.spill [r28] = f28, 0x80 |
| 379 | stf.spill [r29] = f29, 0x80 |
376 | stf.spill [r29] = f29, 0x80 |
| 380 | stf.spill [r30] = f30, 0x80 |
377 | stf.spill [r30] = f30, 0x80 |
| 381 | stf.spill [r31] = f31, 0x80 ;; |
378 | stf.spill [r31] = f31, 0x80 ;; |
| 382 | 379 | ||
| 383 | mov loc47 = ar.fpsr /* preserve floating point status register */ |
380 | mov loc47 = ar.fpsr /* preserve floating point status register */ |
| 384 | 381 | ||
| 385 | /* 9. skipped (will not enable interrupts) */ |
382 | /* 9. skipped (will not enable interrupts) */ |
| 386 | /* |
383 | /* |
| 387 | * ssm PSR_I_MASK |
384 | * ssm PSR_I_MASK |
| 388 | * ;; |
385 | * ;; |
| 389 | * srlz.d |
386 | * srlz.d |
| 390 | */ |
387 | */ |
| 391 | 388 | ||
| 392 | /* 10. call handler */ |
389 | /* 10. call handler */ |
| 393 | movl r1 = _hardcoded_load_address |
390 | movl r1 = _hardcoded_load_address |
| 394 | 391 | ||
| 395 | mov b1 = loc2 |
392 | mov b1 = loc2 |
| 396 | br.call.sptk.many b0 = b1 |
393 | br.call.sptk.many b0 = b1 |
| 397 | 394 | ||
| 398 | /* 11. return from handler */ |
395 | /* 11. return from handler */ |
| 399 | 0: |
396 | 0: |
| 400 | 397 | ||
| 401 | /* 12. skipped (will not disable interrupts) */ |
398 | /* 12. skipped (will not disable interrupts) */ |
| 402 | /* |
399 | /* |
| 403 | * rsm PSR_I_MASK |
400 | * rsm PSR_I_MASK |
| 404 | * ;; |
401 | * ;; |
| 405 | * srlz.d |
402 | * srlz.d |
| 406 | */ |
403 | */ |
| 407 | 404 | ||
| 408 | /* 13. restore general and floating-point registers */ |
405 | /* 13. restore general and floating-point registers */ |
| 409 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
406 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
| 410 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
407 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
| 411 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
408 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
| 412 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
409 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
| 413 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
410 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
| 414 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
411 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
| 415 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
412 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
| 416 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
413 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
| 417 | 414 | ||
| 418 | ldf.fill f2 = [r26], 0x80 |
415 | ldf.fill f2 = [r26], 0x80 |
| 419 | ldf.fill f3 = [r27], 0x80 |
416 | ldf.fill f3 = [r27], 0x80 |
| 420 | ldf.fill f4 = [r28], 0x80 |
417 | ldf.fill f4 = [r28], 0x80 |
| 421 | ldf.fill f5 = [r29], 0x80 |
418 | ldf.fill f5 = [r29], 0x80 |
| 422 | ldf.fill f6 = [r30], 0x80 |
419 | ldf.fill f6 = [r30], 0x80 |
| 423 | ldf.fill f7 = [r31], 0x80 ;; |
420 | ldf.fill f7 = [r31], 0x80 ;; |
| 424 | 421 | ||
| 425 | ldf.fill f8 = [r24], 0x80 |
422 | ldf.fill f8 = [r24], 0x80 |
| 426 | ldf.fill f9 = [r25], 0x80 |
423 | ldf.fill f9 = [r25], 0x80 |
| 427 | ldf.fill f10 = [r26], 0x80 |
424 | ldf.fill f10 = [r26], 0x80 |
| 428 | ldf.fill f11 = [r27], 0x80 |
425 | ldf.fill f11 = [r27], 0x80 |
| 429 | ldf.fill f12 = [r28], 0x80 |
426 | ldf.fill f12 = [r28], 0x80 |
| 430 | ldf.fill f13 = [r29], 0x80 |
427 | ldf.fill f13 = [r29], 0x80 |
| 431 | ldf.fill f14 = [r30], 0x80 |
428 | ldf.fill f14 = [r30], 0x80 |
| 432 | ldf.fill f15 = [r31], 0x80 ;; |
429 | ldf.fill f15 = [r31], 0x80 ;; |
| 433 | 430 | ||
| 434 | ldf.fill f16 = [r24], 0x80 |
431 | ldf.fill f16 = [r24], 0x80 |
| 435 | ldf.fill f17 = [r25], 0x80 |
432 | ldf.fill f17 = [r25], 0x80 |
| 436 | ldf.fill f18 = [r26], 0x80 |
433 | ldf.fill f18 = [r26], 0x80 |
| 437 | ldf.fill f19 = [r27], 0x80 |
434 | ldf.fill f19 = [r27], 0x80 |
| 438 | ldf.fill f20 = [r28], 0x80 |
435 | ldf.fill f20 = [r28], 0x80 |
| 439 | ldf.fill f21 = [r29], 0x80 |
436 | ldf.fill f21 = [r29], 0x80 |
| 440 | ldf.fill f22 = [r30], 0x80 |
437 | ldf.fill f22 = [r30], 0x80 |
| 441 | ldf.fill f23 = [r31], 0x80 ;; |
438 | ldf.fill f23 = [r31], 0x80 ;; |
| 442 | 439 | ||
| 443 | ldf.fill f24 = [r24], 0x80 |
440 | ldf.fill f24 = [r24], 0x80 |
| 444 | ldf.fill f25 = [r25], 0x80 |
441 | ldf.fill f25 = [r25], 0x80 |
| 445 | ldf.fill f26 = [r26], 0x80 |
442 | ldf.fill f26 = [r26], 0x80 |
| 446 | ldf.fill f27 = [r27], 0x80 |
443 | ldf.fill f27 = [r27], 0x80 |
| 447 | ldf.fill f28 = [r28], 0x80 |
444 | ldf.fill f28 = [r28], 0x80 |
| 448 | ldf.fill f29 = [r29], 0x80 |
445 | ldf.fill f29 = [r29], 0x80 |
| 449 | ldf.fill f30 = [r30], 0x80 |
446 | ldf.fill f30 = [r30], 0x80 |
| 450 | ldf.fill f31 = [r31], 0x80 ;; |
447 | ldf.fill f31 = [r31], 0x80 ;; |
| 451 | 448 | ||
| 452 | mov r1 = loc17 |
449 | mov r1 = loc17 |
| 453 | mov r2 = loc18 |
450 | mov r2 = loc18 |
| 454 | mov r3 = loc19 |
451 | mov r3 = loc19 |
| 455 | mov r4 = loc20 |
452 | mov r4 = loc20 |
| 456 | mov r5 = loc21 |
453 | mov r5 = loc21 |
| 457 | mov r6 = loc22 |
454 | mov r6 = loc22 |
| 458 | mov r7 = loc23 |
455 | mov r7 = loc23 |
| 459 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
456 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
| 460 | mov r9 = loc25 |
457 | mov r9 = loc25 |
| 461 | mov r10 = loc26 |
458 | mov r10 = loc26 |
| 462 | mov r11 = loc27 |
459 | mov r11 = loc27 |
| 463 | /* skip r12 (stack pointer) */ |
460 | /* skip r12 (stack pointer) */ |
| 464 | mov r13 = loc28 |
461 | mov r13 = loc28 |
| 465 | mov r14 = loc29 |
462 | mov r14 = loc29 |
| 466 | mov r15 = loc30 |
463 | mov r15 = loc30 |
| 467 | mov r16 = loc31 |
464 | mov r16 = loc31 |
| 468 | mov r17 = loc32 |
465 | mov r17 = loc32 |
| 469 | mov r18 = loc33 |
466 | mov r18 = loc33 |
| 470 | mov r19 = loc34 |
467 | mov r19 = loc34 |
| 471 | mov r20 = loc35 |
468 | mov r20 = loc35 |
| 472 | mov r21 = loc36 |
469 | mov r21 = loc36 |
| 473 | mov r22 = loc37 |
470 | mov r22 = loc37 |
| 474 | mov r23 = loc38 |
471 | mov r23 = loc38 |
| 475 | mov r24 = loc39 |
472 | mov r24 = loc39 |
| 476 | mov r25 = loc40 |
473 | mov r25 = loc40 |
| 477 | mov r26 = loc41 |
474 | mov r26 = loc41 |
| 478 | mov r27 = loc42 |
475 | mov r27 = loc42 |
| 479 | mov r28 = loc43 |
476 | mov r28 = loc43 |
| 480 | mov r29 = loc44 |
477 | mov r29 = loc44 |
| 481 | mov r30 = loc45 |
478 | mov r30 = loc45 |
| 482 | mov r31 = loc46 |
479 | mov r31 = loc46 |
| 483 | 480 | ||
| 484 | mov ar.fpsr = loc47 /* restore floating point status register */ |
481 | mov ar.fpsr = loc47 /* restore floating point status register */ |
| 485 | 482 | ||
| 486 | /* 14. restore branch and application registers */ |
483 | /* 14. restore branch and application registers */ |
| 487 | mov ar.unat = loc3 |
484 | mov ar.unat = loc3 |
| 488 | mov ar.lc = loc4 |
485 | mov ar.lc = loc4 |
| 489 | mov ar.ec = loc5 |
486 | mov ar.ec = loc5 |
| 490 | mov ar.ccv = loc6 |
487 | mov ar.ccv = loc6 |
| 491 | mov ar.csd = loc7 |
488 | mov ar.csd = loc7 |
| 492 | mov ar.ssd = loc8 |
489 | mov ar.ssd = loc8 |
| 493 | 490 | ||
| 494 | mov b0 = loc9 |
491 | mov b0 = loc9 |
| 495 | mov b1 = loc10 |
492 | mov b1 = loc10 |
| 496 | mov b2 = loc11 |
493 | mov b2 = loc11 |
| 497 | mov b3 = loc12 |
494 | mov b3 = loc12 |
| 498 | mov b4 = loc13 |
495 | mov b4 = loc13 |
| 499 | mov b5 = loc14 |
496 | mov b5 = loc14 |
| 500 | mov b6 = loc15 |
497 | mov b6 = loc15 |
| 501 | mov b7 = loc16 |
498 | mov b7 = loc16 |
| 502 | 499 | ||
| 503 | /* 15. disable PSR.ic and switch to bank 0 */ |
500 | /* 15. disable PSR.ic and switch to bank 0 */ |
| 504 | rsm PSR_IC_MASK |
501 | rsm PSR_IC_MASK |
| 505 | bsw.0 ;; |
502 | bsw.0 ;; |
| 506 | srlz.d |
503 | srlz.d |
| 507 | 504 | ||
| 508 | mov R_RET = loc1 |
505 | mov R_RET = loc1 |
| 509 | mov ar.pfs = loc0 |
506 | mov ar.pfs = loc0 |
| 510 | br.ret.sptk.many b0 |
507 | br.ret.sptk.many b0 |
| 511 | 508 | ||
| 512 | .global ivt |
509 | .global ivt |
| 513 | .align 32768 |
510 | .align 32768 |
| 514 | ivt: |
511 | ivt: |
| 515 | HEAVYWEIGHT_HANDLER 0x0000 |
512 | HEAVYWEIGHT_HANDLER 0x0000 |
| 516 | HEAVYWEIGHT_HANDLER 0x0400 |
513 | HEAVYWEIGHT_HANDLER 0x0400 |
| 517 | HEAVYWEIGHT_HANDLER 0x0800 |
514 | HEAVYWEIGHT_HANDLER 0x0800 |
| 518 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
515 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
| 519 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
516 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
| 520 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
517 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
| 521 | HEAVYWEIGHT_HANDLER 0x1800 |
518 | HEAVYWEIGHT_HANDLER 0x1800 |
| 522 | HEAVYWEIGHT_HANDLER 0x1c00 |
519 | HEAVYWEIGHT_HANDLER 0x1c00 |
| 523 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
520 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
| 524 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
521 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
| 525 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
522 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
| 526 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
523 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
| 527 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
524 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
| 528 | HEAVYWEIGHT_HANDLER 0x3400 |
525 | HEAVYWEIGHT_HANDLER 0x3400 |
| 529 | HEAVYWEIGHT_HANDLER 0x3800 |
526 | HEAVYWEIGHT_HANDLER 0x3800 |
| 530 | HEAVYWEIGHT_HANDLER 0x3c00 |
527 | HEAVYWEIGHT_HANDLER 0x3c00 |
| 531 | HEAVYWEIGHT_HANDLER 0x4000 |
528 | HEAVYWEIGHT_HANDLER 0x4000 |
| 532 | HEAVYWEIGHT_HANDLER 0x4400 |
529 | HEAVYWEIGHT_HANDLER 0x4400 |
| 533 | HEAVYWEIGHT_HANDLER 0x4800 |
530 | HEAVYWEIGHT_HANDLER 0x4800 |
| 534 | HEAVYWEIGHT_HANDLER 0x4c00 |
531 | HEAVYWEIGHT_HANDLER 0x4c00 |
| 535 | 532 | ||
| 536 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
533 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
| 537 | HEAVYWEIGHT_HANDLER 0x5100 |
534 | HEAVYWEIGHT_HANDLER 0x5100 |
| 538 | HEAVYWEIGHT_HANDLER 0x5200 |
535 | HEAVYWEIGHT_HANDLER 0x5200 |
| 539 | HEAVYWEIGHT_HANDLER 0x5300 |
536 | HEAVYWEIGHT_HANDLER 0x5300 |
| 540 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
537 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
| 541 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
538 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
| 542 | HEAVYWEIGHT_HANDLER 0x5600 |
539 | HEAVYWEIGHT_HANDLER 0x5600 |
| 543 | HEAVYWEIGHT_HANDLER 0x5700 |
540 | HEAVYWEIGHT_HANDLER 0x5700 |
| 544 | HEAVYWEIGHT_HANDLER 0x5800 |
541 | HEAVYWEIGHT_HANDLER 0x5800 |
| 545 | HEAVYWEIGHT_HANDLER 0x5900 |
542 | HEAVYWEIGHT_HANDLER 0x5900 |
| 546 | HEAVYWEIGHT_HANDLER 0x5a00 |
543 | HEAVYWEIGHT_HANDLER 0x5a00 |
| 547 | HEAVYWEIGHT_HANDLER 0x5b00 |
544 | HEAVYWEIGHT_HANDLER 0x5b00 |
| 548 | HEAVYWEIGHT_HANDLER 0x5c00 |
545 | HEAVYWEIGHT_HANDLER 0x5c00 |
| 549 | HEAVYWEIGHT_HANDLER 0x5d00 |
546 | HEAVYWEIGHT_HANDLER 0x5d00 |
| 550 | HEAVYWEIGHT_HANDLER 0x5e00 |
547 | HEAVYWEIGHT_HANDLER 0x5e00 |
| 551 | HEAVYWEIGHT_HANDLER 0x5f00 |
548 | HEAVYWEIGHT_HANDLER 0x5f00 |
| 552 | 549 | ||
| 553 | HEAVYWEIGHT_HANDLER 0x6000 |
550 | HEAVYWEIGHT_HANDLER 0x6000 |
| 554 | HEAVYWEIGHT_HANDLER 0x6100 |
551 | HEAVYWEIGHT_HANDLER 0x6100 |
| 555 | HEAVYWEIGHT_HANDLER 0x6200 |
552 | HEAVYWEIGHT_HANDLER 0x6200 |
| 556 | HEAVYWEIGHT_HANDLER 0x6300 |
553 | HEAVYWEIGHT_HANDLER 0x6300 |
| 557 | HEAVYWEIGHT_HANDLER 0x6400 |
554 | HEAVYWEIGHT_HANDLER 0x6400 |
| 558 | HEAVYWEIGHT_HANDLER 0x6500 |
555 | HEAVYWEIGHT_HANDLER 0x6500 |
| 559 | HEAVYWEIGHT_HANDLER 0x6600 |
556 | HEAVYWEIGHT_HANDLER 0x6600 |
| 560 | HEAVYWEIGHT_HANDLER 0x6700 |
557 | HEAVYWEIGHT_HANDLER 0x6700 |
| 561 | HEAVYWEIGHT_HANDLER 0x6800 |
558 | HEAVYWEIGHT_HANDLER 0x6800 |
| 562 | HEAVYWEIGHT_HANDLER 0x6900 |
559 | HEAVYWEIGHT_HANDLER 0x6900 |
| 563 | HEAVYWEIGHT_HANDLER 0x6a00 |
560 | HEAVYWEIGHT_HANDLER 0x6a00 |
| 564 | HEAVYWEIGHT_HANDLER 0x6b00 |
561 | HEAVYWEIGHT_HANDLER 0x6b00 |
| 565 | HEAVYWEIGHT_HANDLER 0x6c00 |
562 | HEAVYWEIGHT_HANDLER 0x6c00 |
| 566 | HEAVYWEIGHT_HANDLER 0x6d00 |
563 | HEAVYWEIGHT_HANDLER 0x6d00 |
| 567 | HEAVYWEIGHT_HANDLER 0x6e00 |
564 | HEAVYWEIGHT_HANDLER 0x6e00 |
| 568 | HEAVYWEIGHT_HANDLER 0x6f00 |
565 | HEAVYWEIGHT_HANDLER 0x6f00 |
| 569 | 566 | ||
| 570 | HEAVYWEIGHT_HANDLER 0x7000 |
567 | HEAVYWEIGHT_HANDLER 0x7000 |
| 571 | HEAVYWEIGHT_HANDLER 0x7100 |
568 | HEAVYWEIGHT_HANDLER 0x7100 |
| 572 | HEAVYWEIGHT_HANDLER 0x7200 |
569 | HEAVYWEIGHT_HANDLER 0x7200 |
| 573 | HEAVYWEIGHT_HANDLER 0x7300 |
570 | HEAVYWEIGHT_HANDLER 0x7300 |
| 574 | HEAVYWEIGHT_HANDLER 0x7400 |
571 | HEAVYWEIGHT_HANDLER 0x7400 |
| 575 | HEAVYWEIGHT_HANDLER 0x7500 |
572 | HEAVYWEIGHT_HANDLER 0x7500 |
| 576 | HEAVYWEIGHT_HANDLER 0x7600 |
573 | HEAVYWEIGHT_HANDLER 0x7600 |
| 577 | HEAVYWEIGHT_HANDLER 0x7700 |
574 | HEAVYWEIGHT_HANDLER 0x7700 |
| 578 | HEAVYWEIGHT_HANDLER 0x7800 |
575 | HEAVYWEIGHT_HANDLER 0x7800 |
| 579 | HEAVYWEIGHT_HANDLER 0x7900 |
576 | HEAVYWEIGHT_HANDLER 0x7900 |
| 580 | HEAVYWEIGHT_HANDLER 0x7a00 |
577 | HEAVYWEIGHT_HANDLER 0x7a00 |
| 581 | HEAVYWEIGHT_HANDLER 0x7b00 |
578 | HEAVYWEIGHT_HANDLER 0x7b00 |
| 582 | HEAVYWEIGHT_HANDLER 0x7c00 |
579 | HEAVYWEIGHT_HANDLER 0x7c00 |
| 583 | HEAVYWEIGHT_HANDLER 0x7d00 |
580 | HEAVYWEIGHT_HANDLER 0x7d00 |
| 584 | HEAVYWEIGHT_HANDLER 0x7e00 |
581 | HEAVYWEIGHT_HANDLER 0x7e00 |
| 585 | HEAVYWEIGHT_HANDLER 0x7f00 |
582 | HEAVYWEIGHT_HANDLER 0x7f00 |
| 586 | 583 | ||