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| Rev 1023 | Rev 1053 | ||
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| Line 30... | Line 30... | ||
| 30 | #include <arch/stack.h> |
30 | #include <arch/stack.h> |
| 31 | #include <arch/register.h> |
31 | #include <arch/register.h> |
| 32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
| 33 | #include <align.h> |
33 | #include <align.h> |
| 34 | 34 | ||
| - | 35 | ||
| - | 36 | #define FRS_TO_SAVE 30 |
|
| - | 37 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
|
| 35 | #define STACK_ITEMS 19 |
38 | //#define STACK_ITEMS 19 |
| - | 39 | /* 30*2 for FPU registers */ |
|
| 36 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
40 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
| 37 | 41 | ||
| 38 | #if (STACK_ITEMS % 2 == 0) |
42 | #if (STACK_ITEMS % 2 == 0) |
| 39 | # define STACK_FRAME_BIAS 8 |
43 | # define STACK_FRAME_BIAS 8 |
| 40 | #else |
44 | #else |
| Line 76... | Line 80... | ||
| 76 | /* 1. copy interrupt registers into bank 0 */ |
80 | /* 1. copy interrupt registers into bank 0 */ |
| 77 | 81 | ||
| 78 | /* |
82 | /* |
| 79 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
83 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
| 80 | */ |
84 | */ |
| - | 85 | ||
| - | 86 | /*Set up FPU as in interrupred*/ |
|
| - | 87 | mov r24=psr |
|
| - | 88 | mov r25=cr.ipsr |
|
| - | 89 | mov r26=(PSR_DFH_MASK) |
|
| - | 90 | mov r27=(~(PSR_DFH_MASK));; |
|
| - | 91 | and r26=r25,r26 |
|
| - | 92 | and r24=r24,r27;; |
|
| - | 93 | or r24=r24,r26;; |
|
| - | 94 | mov psr.l=r24;; |
|
| - | 95 | srlz.i |
|
| - | 96 | srlz.d;; |
|
| - | 97 | ||
| 81 | mov r24 = cr.iip |
98 | mov r24 = cr.iip |
| 82 | mov r25 = cr.ipsr |
99 | mov r25 = cr.ipsr |
| 83 | mov r26 = cr.iipa |
100 | mov r26 = cr.iipa |
| 84 | mov r27 = cr.isr |
101 | mov r27 = cr.isr |
| 85 | mov r28 = cr.ifa |
102 | mov r28 = cr.ifa |
| Line 193... | Line 210... | ||
| 193 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
210 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
| 194 | 211 | ||
| 195 | /* 16. RSE switch to interrupted context */ |
212 | /* 16. RSE switch to interrupted context */ |
| 196 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
213 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
| 197 | 214 | ||
| 198 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;; |
215 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
| 199 | 216 | ||
| 200 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
217 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
| 201 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
218 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
| 202 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
219 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
| 203 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
220 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
| Line 228... | Line 245... | ||
| 228 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
245 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
| 229 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
246 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
| 230 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
247 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
| 231 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
248 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
| 232 | 249 | ||
| 233 | mov cr.iip = r24 |
250 | mov cr.iip = r24;; |
| 234 | mov cr.ipsr = r25 |
- | |
| 235 | mov cr.iipa = r26 |
251 | mov cr.iipa = r26 |
| 236 | mov cr.isr = r27 |
252 | mov cr.isr = r27 |
| 237 | mov cr.ifa = r28 |
253 | mov cr.ifa = r28 |
| - | 254 | /*Set up FPU as in exception*/ |
|
| - | 255 | mov r24=psr |
|
| - | 256 | mov r26=(PSR_DFH_MASK) |
|
| - | 257 | mov r27=(~(PSR_DFH_MASK));; |
|
| - | 258 | and r25=r25,r27 |
|
| - | 259 | and r24=r24,r26;; |
|
| - | 260 | or r25=r25,r24;; |
|
| - | 261 | mov cr.ipsr = r25 |
|
| - | 262 | ||
| 238 | 263 | ||
| 239 | /* 18. restore predicate registers from memory stack */ |
264 | /* 18. restore predicate registers from memory stack */ |
| 240 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
265 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
| 241 | mov pr = r29 |
266 | mov pr = r29 |
| 242 | 267 | ||
| Line 313... | Line 338... | ||
| 313 | mov loc43 = r28 |
338 | mov loc43 = r28 |
| 314 | mov loc44 = r29 |
339 | mov loc44 = r29 |
| 315 | mov loc45 = r30 |
340 | mov loc45 = r30 |
| 316 | mov loc46 = r31 |
341 | mov loc46 = r31 |
| 317 | 342 | ||
| - | 343 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
|
| - | 344 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
|
| - | 345 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
|
| - | 346 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
|
| - | 347 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
|
| - | 348 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
|
| - | 349 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
|
| - | 350 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
|
| - | 351 | add r24=r12,r24 |
|
| - | 352 | add r25=r12,r25 |
|
| - | 353 | add r26=r12,r26 |
|
| - | 354 | add r27=r12,r27 |
|
| - | 355 | add r28=r12,r28 |
|
| - | 356 | add r29=r12,r29 |
|
| - | 357 | add r30=r12,r30 |
|
| - | 358 | add r31=r12,r31;; |
|
| - | 359 | ||
| - | 360 | stf.spill [r26]=f2,0x80 |
|
| - | 361 | stf.spill [r27]=f3,0x80 |
|
| - | 362 | stf.spill [r28]=f4,0x80 |
|
| - | 363 | stf.spill [r29]=f5,0x80 |
|
| - | 364 | stf.spill [r30]=f6,0x80 |
|
| - | 365 | stf.spill [r31]=f7,0x80;; |
|
| - | 366 | ||
| - | 367 | stf.spill [r24]=f8,0x80 |
|
| - | 368 | stf.spill [r25]=f9,0x80 |
|
| - | 369 | stf.spill [r26]=f10,0x80 |
|
| - | 370 | stf.spill [r27]=f11,0x80 |
|
| - | 371 | stf.spill [r28]=f12,0x80 |
|
| - | 372 | stf.spill [r29]=f13,0x80 |
|
| - | 373 | stf.spill [r30]=f14,0x80 |
|
| - | 374 | stf.spill [r31]=f15,0x80;; |
|
| - | 375 | ||
| - | 376 | stf.spill [r24]=f16,0x80 |
|
| - | 377 | stf.spill [r25]=f17,0x80 |
|
| - | 378 | stf.spill [r26]=f18,0x80 |
|
| - | 379 | stf.spill [r27]=f19,0x80 |
|
| - | 380 | stf.spill [r28]=f20,0x80 |
|
| - | 381 | stf.spill [r29]=f21,0x80 |
|
| - | 382 | stf.spill [r30]=f22,0x80 |
|
| - | 383 | stf.spill [r31]=f23,0x80;; |
|
| - | 384 | ||
| - | 385 | stf.spill [r24]=f24,0x80 |
|
| - | 386 | stf.spill [r25]=f25,0x80 |
|
| - | 387 | stf.spill [r26]=f26,0x80 |
|
| - | 388 | stf.spill [r27]=f27,0x80 |
|
| - | 389 | stf.spill [r28]=f28,0x80 |
|
| - | 390 | stf.spill [r29]=f29,0x80 |
|
| - | 391 | stf.spill [r30]=f30,0x80 |
|
| - | 392 | stf.spill [r31]=f31,0x80;; |
|
| - | 393 | ||
| 318 | /* preserve Floating point status register */ |
394 | /* preserve Floating point status register */ |
| 319 | mov loc47 = ar.fpsr |
395 | mov loc47 = ar.fpsr |
| 320 | 396 | ||
| 321 | /* 9. skipped (will not enable interrupts) */ |
397 | /* 9. skipped (will not enable interrupts) */ |
| 322 | /* |
398 | /* |
| Line 341... | Line 417... | ||
| 341 | * srlz.d |
417 | * srlz.d |
| 342 | */ |
418 | */ |
| 343 | 419 | ||
| 344 | /* 13. restore general and floating-point registers */ |
420 | /* 13. restore general and floating-point registers */ |
| 345 | /* TODO: restore floating-point context */ |
421 | /* TODO: restore floating-point context */ |
| - | 422 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
|
| - | 423 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
|
| - | 424 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
|
| - | 425 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
|
| - | 426 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
|
| - | 427 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
|
| - | 428 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
|
| - | 429 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
|
| - | 430 | add r24=r12,r24 |
|
| - | 431 | add r25=r12,r25 |
|
| - | 432 | add r26=r12,r26 |
|
| - | 433 | add r27=r12,r27 |
|
| - | 434 | add r28=r12,r28 |
|
| - | 435 | add r29=r12,r29 |
|
| - | 436 | add r30=r12,r30 |
|
| - | 437 | add r31=r12,r31;; |
|
| - | 438 | ||
| - | 439 | ||
| - | 440 | ldf.fill f2=[r26],0x80 |
|
| - | 441 | ldf.fill f3=[r27],0x80 |
|
| - | 442 | ldf.fill f4=[r28],0x80 |
|
| - | 443 | ldf.fill f5=[r29],0x80 |
|
| - | 444 | ldf.fill f6=[r30],0x80 |
|
| - | 445 | ldf.fill f7=[r31],0x80;; |
|
| - | 446 | ||
| - | 447 | ldf.fill f8=[r24],0x80 |
|
| - | 448 | ldf.fill f9=[r25],0x80 |
|
| - | 449 | ldf.fill f10=[r26],0x80 |
|
| - | 450 | ldf.fill f11=[r27],0x80 |
|
| - | 451 | ldf.fill f12=[r28],0x80 |
|
| - | 452 | ldf.fill f13=[r29],0x80 |
|
| - | 453 | ldf.fill f14=[r30],0x80 |
|
| - | 454 | ldf.fill f15=[r31],0x80;; |
|
| - | 455 | ||
| - | 456 | ldf.fill f16=[r24],0x80 |
|
| - | 457 | ldf.fill f17=[r25],0x80 |
|
| - | 458 | ldf.fill f18=[r26],0x80 |
|
| - | 459 | ldf.fill f19=[r27],0x80 |
|
| - | 460 | ldf.fill f20=[r28],0x80 |
|
| - | 461 | ldf.fill f21=[r29],0x80 |
|
| - | 462 | ldf.fill f22=[r30],0x80 |
|
| - | 463 | ldf.fill f23=[r31],0x80;; |
|
| - | 464 | ||
| - | 465 | ldf.fill f24=[r24],0x80 |
|
| - | 466 | ldf.fill f25=[r25],0x80 |
|
| - | 467 | ldf.fill f26=[r26],0x80 |
|
| - | 468 | ldf.fill f27=[r27],0x80 |
|
| - | 469 | ldf.fill f28=[r28],0x80 |
|
| - | 470 | ldf.fill f29=[r29],0x80 |
|
| - | 471 | ldf.fill f30=[r30],0x80 |
|
| - | 472 | ldf.fill f31=[r31],0x80;; |
|
| - | 473 | ||
| - | 474 | ||
| 346 | mov r1 = loc17 |
475 | mov r1 = loc17 |
| 347 | mov r2 = loc18 |
476 | mov r2 = loc18 |
| 348 | mov r3 = loc19 |
477 | mov r3 = loc19 |
| 349 | mov r4 = loc20 |
478 | mov r4 = loc20 |
| 350 | mov r5 = loc21 |
479 | mov r5 = loc21 |
| Line 476... | Line 605... | ||
| 476 | HEAVYWEIGHT_HANDLER 0x7b00 |
605 | HEAVYWEIGHT_HANDLER 0x7b00 |
| 477 | HEAVYWEIGHT_HANDLER 0x7c00 |
606 | HEAVYWEIGHT_HANDLER 0x7c00 |
| 478 | HEAVYWEIGHT_HANDLER 0x7d00 |
607 | HEAVYWEIGHT_HANDLER 0x7d00 |
| 479 | HEAVYWEIGHT_HANDLER 0x7e00 |
608 | HEAVYWEIGHT_HANDLER 0x7e00 |
| 480 | HEAVYWEIGHT_HANDLER 0x7f00 |
609 | HEAVYWEIGHT_HANDLER 0x7f00 |
| - | 610 | ||
| - | 611 | ||
| - | 612 | ||
| - | 613 | ||